use atomic bools in std lib
Vexu
parent
8dc188ebe0
commit
ee5b00a8b9
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@ -1,7 +1,5 @@
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const std = @import("../std.zig");
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const builtin = @import("builtin");
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const AtomicOrder = builtin.AtomicOrder;
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const AtomicRmwOp = builtin.AtomicRmwOp;
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const assert = std.debug.assert;
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const expect = std.testing.expect;
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@ -149,7 +147,7 @@ const Context = struct {
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put_sum: isize,
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get_sum: isize,
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get_count: usize,
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puts_done: u8, // TODO make this a bool
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puts_done: bool,
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};
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// TODO add lazy evaluated build options and then put puts_per_thread behind
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@ -173,7 +171,7 @@ test "std.atomic.Queue" {
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.queue = &queue,
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.put_sum = 0,
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.get_sum = 0,
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.puts_done = 0,
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.puts_done = false,
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.get_count = 0,
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};
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@ -186,7 +184,7 @@ test "std.atomic.Queue" {
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}
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}
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expect(!context.queue.isEmpty());
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context.puts_done = 1;
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context.puts_done = true;
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{
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var i: usize = 0;
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while (i < put_thread_count) : (i += 1) {
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@ -208,7 +206,7 @@ test "std.atomic.Queue" {
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for (putters) |t|
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t.wait();
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@atomicStore(u8, &context.puts_done, 1, AtomicOrder.SeqCst);
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@atomicStore(bool, &context.puts_done, true, .SeqCst);
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for (getters) |t|
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t.wait();
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@ -235,25 +233,25 @@ fn startPuts(ctx: *Context) u8 {
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std.time.sleep(1); // let the os scheduler be our fuzz
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const x = @bitCast(i32, r.random.scalar(u32));
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const node = ctx.allocator.create(Queue(i32).Node) catch unreachable;
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node.* = Queue(i32).Node{
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node.* = .{
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.prev = undefined,
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.next = undefined,
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.data = x,
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};
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ctx.queue.put(node);
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_ = @atomicRmw(isize, &ctx.put_sum, builtin.AtomicRmwOp.Add, x, AtomicOrder.SeqCst);
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_ = @atomicRmw(isize, &ctx.put_sum, .Add, x, .SeqCst);
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}
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return 0;
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}
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fn startGets(ctx: *Context) u8 {
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while (true) {
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const last = @atomicLoad(u8, &ctx.puts_done, builtin.AtomicOrder.SeqCst) == 1;
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const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst);
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while (ctx.queue.get()) |node| {
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std.time.sleep(1); // let the os scheduler be our fuzz
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_ = @atomicRmw(isize, &ctx.get_sum, builtin.AtomicRmwOp.Add, node.data, builtin.AtomicOrder.SeqCst);
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_ = @atomicRmw(usize, &ctx.get_count, builtin.AtomicRmwOp.Add, 1, builtin.AtomicOrder.SeqCst);
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_ = @atomicRmw(isize, &ctx.get_sum, .Add, node.data, .SeqCst);
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_ = @atomicRmw(usize, &ctx.get_count, .Add, 1, .SeqCst);
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}
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if (last) return 0;
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@ -1,6 +1,5 @@
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const assert = std.debug.assert;
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const builtin = @import("builtin");
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const AtomicOrder = builtin.AtomicOrder;
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const expect = std.testing.expect;
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/// Many reader, many writer, non-allocating, thread-safe
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@ -11,7 +10,7 @@ pub fn Stack(comptime T: type) type {
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root: ?*Node,
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lock: @TypeOf(lock_init),
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const lock_init = if (builtin.single_threaded) {} else @as(u8, 0);
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const lock_init = if (builtin.single_threaded) {} else false;
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pub const Self = @This();
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@ -31,7 +30,7 @@ pub fn Stack(comptime T: type) type {
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/// being the first item in the stack, returns the other item that was there.
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pub fn pushFirst(self: *Self, node: *Node) ?*Node {
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node.next = null;
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return @cmpxchgStrong(?*Node, &self.root, null, node, AtomicOrder.SeqCst, AtomicOrder.SeqCst);
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return @cmpxchgStrong(?*Node, &self.root, null, node, .SeqCst, .SeqCst);
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}
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pub fn push(self: *Self, node: *Node) void {
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@ -39,8 +38,8 @@ pub fn Stack(comptime T: type) type {
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node.next = self.root;
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self.root = node;
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} else {
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while (@atomicRmw(u8, &self.lock, builtin.AtomicRmwOp.Xchg, 1, AtomicOrder.SeqCst) != 0) {}
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defer assert(@atomicRmw(u8, &self.lock, builtin.AtomicRmwOp.Xchg, 0, AtomicOrder.SeqCst) == 1);
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while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {}
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defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true);
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node.next = self.root;
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self.root = node;
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@ -53,8 +52,8 @@ pub fn Stack(comptime T: type) type {
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self.root = root.next;
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return root;
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} else {
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while (@atomicRmw(u8, &self.lock, builtin.AtomicRmwOp.Xchg, 1, AtomicOrder.SeqCst) != 0) {}
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defer assert(@atomicRmw(u8, &self.lock, builtin.AtomicRmwOp.Xchg, 0, AtomicOrder.SeqCst) == 1);
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while (@atomicRmw(bool, &self.lock, .Xchg, true, .SeqCst) != false) {}
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defer assert(@atomicRmw(bool, &self.lock, .Xchg, false, .SeqCst) == true);
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const root = self.root orelse return null;
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self.root = root.next;
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@ -63,7 +62,7 @@ pub fn Stack(comptime T: type) type {
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}
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pub fn isEmpty(self: *Self) bool {
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return @atomicLoad(?*Node, &self.root, AtomicOrder.SeqCst) == null;
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return @atomicLoad(?*Node, &self.root, .SeqCst) == null;
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}
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};
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}
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@ -75,7 +74,7 @@ const Context = struct {
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put_sum: isize,
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get_sum: isize,
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get_count: usize,
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puts_done: u8, // TODO make this a bool
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puts_done: bool,
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};
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// TODO add lazy evaluated build options and then put puts_per_thread behind
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// some option such as: "AggressiveMultithreadedFuzzTest". In the AppVeyor
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@ -98,7 +97,7 @@ test "std.atomic.stack" {
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.stack = &stack,
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.put_sum = 0,
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.get_sum = 0,
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.puts_done = 0,
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.puts_done = false,
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.get_count = 0,
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};
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@ -109,7 +108,7 @@ test "std.atomic.stack" {
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expect(startPuts(&context) == 0);
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}
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}
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context.puts_done = 1;
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context.puts_done = true;
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{
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var i: usize = 0;
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while (i < put_thread_count) : (i += 1) {
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@ -128,7 +127,7 @@ test "std.atomic.stack" {
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for (putters) |t|
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t.wait();
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@atomicStore(u8, &context.puts_done, 1, AtomicOrder.SeqCst);
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@atomicStore(bool, &context.puts_done, true, .SeqCst);
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for (getters) |t|
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t.wait();
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}
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@ -158,19 +157,19 @@ fn startPuts(ctx: *Context) u8 {
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.data = x,
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};
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ctx.stack.push(node);
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_ = @atomicRmw(isize, &ctx.put_sum, builtin.AtomicRmwOp.Add, x, AtomicOrder.SeqCst);
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_ = @atomicRmw(isize, &ctx.put_sum, .Add, x, .SeqCst);
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}
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return 0;
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}
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fn startGets(ctx: *Context) u8 {
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while (true) {
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const last = @atomicLoad(u8, &ctx.puts_done, builtin.AtomicOrder.SeqCst) == 1;
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const last = @atomicLoad(bool, &ctx.puts_done, .SeqCst) == true;
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while (ctx.stack.pop()) |node| {
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std.time.sleep(1); // let the os scheduler be our fuzz
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_ = @atomicRmw(isize, &ctx.get_sum, builtin.AtomicRmwOp.Add, node.data, builtin.AtomicOrder.SeqCst);
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_ = @atomicRmw(usize, &ctx.get_count, builtin.AtomicRmwOp.Add, 1, builtin.AtomicOrder.SeqCst);
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_ = @atomicRmw(isize, &ctx.get_sum, .Add, node.data, .SeqCst);
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_ = @atomicRmw(usize, &ctx.get_count, .Add, 1, .SeqCst);
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}
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if (last) return 0;
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@ -14,8 +14,8 @@ pub fn Channel(comptime T: type) type {
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putters: std.atomic.Queue(PutNode),
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get_count: usize,
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put_count: usize,
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dispatch_lock: u8, // TODO make this a bool
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need_dispatch: u8, // TODO make this a bool
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dispatch_lock: bool,
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need_dispatch: bool,
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// simple fixed size ring buffer
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buffer_nodes: []T,
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@ -62,8 +62,8 @@ pub fn Channel(comptime T: type) type {
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.buffer_len = 0,
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.buffer_nodes = buffer,
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.buffer_index = 0,
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.dispatch_lock = 0,
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.need_dispatch = 0,
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.dispatch_lock = false,
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.need_dispatch = false,
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.getters = std.atomic.Queue(GetNode).init(),
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.putters = std.atomic.Queue(PutNode).init(),
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.or_null_queue = std.atomic.Queue(*std.atomic.Queue(GetNode).Node).init(),
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@ -165,15 +165,15 @@ pub fn Channel(comptime T: type) type {
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fn dispatch(self: *SelfChannel) void {
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// set the "need dispatch" flag
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@atomicStore(u8, &self.need_dispatch, 1, .SeqCst);
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@atomicStore(bool, &self.need_dispatch, true, .SeqCst);
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lock: while (true) {
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// set the lock flag
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const prev_lock = @atomicRmw(u8, &self.dispatch_lock, .Xchg, 1, .SeqCst);
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const prev_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, true, .SeqCst);
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if (prev_lock != 0) return;
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// clear the need_dispatch flag since we're about to do it
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@atomicStore(u8, &self.need_dispatch, 0, .SeqCst);
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@atomicStore(bool, &self.need_dispatch, false, .SeqCst);
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while (true) {
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one_dispatch: {
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@ -250,14 +250,14 @@ pub fn Channel(comptime T: type) type {
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}
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// clear need-dispatch flag
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const need_dispatch = @atomicRmw(u8, &self.need_dispatch, .Xchg, 0, .SeqCst);
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if (need_dispatch != 0) continue;
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const need_dispatch = @atomicRmw(bool, &self.need_dispatch, .Xchg, false, .SeqCst);
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if (need_dispatch) continue;
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const my_lock = @atomicRmw(u8, &self.dispatch_lock, .Xchg, 0, .SeqCst);
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assert(my_lock != 0);
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const my_lock = @atomicRmw(bool, &self.dispatch_lock, .Xchg, false, .SeqCst);
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assert(my_lock);
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// we have to check again now that we unlocked
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if (@atomicLoad(u8, &self.need_dispatch, .SeqCst) != 0) continue :lock;
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if (@atomicLoad(bool, &self.need_dispatch, .SeqCst)) continue :lock;
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return;
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}
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@ -11,9 +11,9 @@ const Loop = std.event.Loop;
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/// Allows only one actor to hold the lock.
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/// TODO: make this API also work in blocking I/O mode.
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pub const Lock = struct {
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shared_bit: u8, // TODO make this a bool
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shared: bool,
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queue: Queue,
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queue_empty_bit: u8, // TODO make this a bool
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queue_empty: bool,
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const Queue = std.atomic.Queue(anyframe);
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@ -31,20 +31,19 @@ pub const Lock = struct {
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}
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// We need to release the lock.
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@atomicStore(u8, &self.lock.queue_empty_bit, 1, .SeqCst);
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@atomicStore(u8, &self.lock.shared_bit, 0, .SeqCst);
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@atomicStore(bool, &self.lock.queue_empty, true, .SeqCst);
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@atomicStore(bool, &self.lock.shared, false, .SeqCst);
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// There might be a queue item. If we know the queue is empty, we can be done,
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// because the other actor will try to obtain the lock.
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// But if there's a queue item, we are the actor which must loop and attempt
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// to grab the lock again.
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if (@atomicLoad(u8, &self.lock.queue_empty_bit, .SeqCst) == 1) {
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if (@atomicLoad(bool, &self.lock.queue_empty, .SeqCst)) {
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return;
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}
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while (true) {
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const old_bit = @atomicRmw(u8, &self.lock.shared_bit, .Xchg, 1, .SeqCst);
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if (old_bit != 0) {
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if (@atomicRmw(bool, &self.lock.shared, .Xchg, true, .SeqCst)) {
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// We did not obtain the lock. Great, the queue is someone else's problem.
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return;
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}
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@ -56,11 +55,11 @@ pub const Lock = struct {
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}
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// Release the lock again.
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@atomicStore(u8, &self.lock.queue_empty_bit, 1, .SeqCst);
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@atomicStore(u8, &self.lock.shared_bit, 0, .SeqCst);
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@atomicStore(bool, &self.lock.queue_empty, true, .SeqCst);
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@atomicStore(bool, &self.lock.shared, false, .SeqCst);
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// Find out if we can be done.
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if (@atomicLoad(u8, &self.lock.queue_empty_bit, .SeqCst) == 1) {
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if (@atomicLoad(bool, &self.lock.queue_empty, .SeqCst)) {
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return;
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}
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}
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@ -69,24 +68,24 @@ pub const Lock = struct {
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pub fn init() Lock {
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return Lock{
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.shared_bit = 0,
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.shared = false,
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.queue = Queue.init(),
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.queue_empty_bit = 1,
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.queue_empty = true,
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};
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}
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pub fn initLocked() Lock {
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return Lock{
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.shared_bit = 1,
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.shared = true,
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.queue = Queue.init(),
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.queue_empty_bit = 1,
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.queue_empty = true,
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};
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}
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/// Must be called when not locked. Not thread safe.
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/// All calls to acquire() and release() must complete before calling deinit().
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pub fn deinit(self: *Lock) void {
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assert(self.shared_bit == 0);
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assert(!self.shared);
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while (self.queue.get()) |node| resume node.data;
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}
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@ -99,12 +98,11 @@ pub const Lock = struct {
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// At this point, we are in the queue, so we might have already been resumed.
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// We set this bit so that later we can rely on the fact, that if queue_empty_bit is 1, some actor
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// We set this bit so that later we can rely on the fact, that if queue_empty == true, some actor
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// will attempt to grab the lock.
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@atomicStore(u8, &self.queue_empty_bit, 0, .SeqCst);
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@atomicStore(bool, &self.queue_empty, false, .SeqCst);
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const old_bit = @atomicRmw(u8, &self.shared_bit, .Xchg, 1, .SeqCst);
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if (old_bit == 0) {
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if (!@atomicRmw(bool, &self.shared, .Xchg, true, .SeqCst)) {
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if (self.queue.get()) |node| {
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// Whether this node is us or someone else, we tail resume it.
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resume node.data;
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@ -16,8 +16,8 @@ pub const RwLock = struct {
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shared_state: State,
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writer_queue: Queue,
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reader_queue: Queue,
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writer_queue_empty_bit: u8, // TODO make this a bool
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reader_queue_empty_bit: u8, // TODO make this a bool
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writer_queue_empty: bool,
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reader_queue_empty: bool,
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reader_lock_count: usize,
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const State = enum(u8) {
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@ -40,7 +40,7 @@ pub const RwLock = struct {
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return;
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}
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@atomicStore(u8, &self.lock.reader_queue_empty_bit, 1, .SeqCst);
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@atomicStore(bool, &self.lock.reader_queue_empty, true, .SeqCst);
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if (@cmpxchgStrong(State, &self.lock.shared_state, .ReadLock, .Unlocked, .SeqCst, .SeqCst) != null) {
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// Didn't unlock. Someone else's problem.
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return;
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@ -62,7 +62,7 @@ pub const RwLock = struct {
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}
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// We need to release the write lock. Check if any readers are waiting to grab the lock.
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if (@atomicLoad(u8, &self.lock.reader_queue_empty_bit, .SeqCst) == 0) {
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if (!@atomicLoad(bool, &self.lock.reader_queue_empty, .SeqCst)) {
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// Switch to a read lock.
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@atomicStore(State, &self.lock.shared_state, .ReadLock, .SeqCst);
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while (self.lock.reader_queue.get()) |node| {
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@ -71,7 +71,7 @@ pub const RwLock = struct {
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return;
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}
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@atomicStore(u8, &self.lock.writer_queue_empty_bit, 1, .SeqCst);
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@atomicStore(bool, &self.lock.writer_queue_empty, true, .SeqCst);
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@atomicStore(State, &self.lock.shared_state, .Unlocked, .SeqCst);
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self.lock.commonPostUnlock();
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@ -79,12 +79,12 @@ pub const RwLock = struct {
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};
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||||
|
||||
pub fn init() RwLock {
|
||||
return RwLock{
|
||||
return .{
|
||||
.shared_state = .Unlocked,
|
||||
.writer_queue = Queue.init(),
|
||||
.writer_queue_empty_bit = 1,
|
||||
.writer_queue_empty = true,
|
||||
.reader_queue = Queue.init(),
|
||||
.reader_queue_empty_bit = 1,
|
||||
.reader_queue_empty = true,
|
||||
.reader_lock_count = 0,
|
||||
};
|
||||
}
|
||||
|
|
@ -111,9 +111,9 @@ pub const RwLock = struct {
|
|||
|
||||
// At this point, we are in the reader_queue, so we might have already been resumed.
|
||||
|
||||
// We set this bit so that later we can rely on the fact, that if reader_queue_empty_bit is 1,
|
||||
// We set this bit so that later we can rely on the fact, that if reader_queue_empty == true,
|
||||
// some actor will attempt to grab the lock.
|
||||
@atomicStore(u8, &self.reader_queue_empty_bit, 0, .SeqCst);
|
||||
@atomicStore(bool, &self.reader_queue_empty, false, .SeqCst);
|
||||
|
||||
// Here we don't care if we are the one to do the locking or if it was already locked for reading.
|
||||
const have_read_lock = if (@cmpxchgStrong(State, &self.shared_state, .Unlocked, .ReadLock, .SeqCst, .SeqCst)) |old_state| old_state == .ReadLock else true;
|
||||
|
|
@ -142,9 +142,9 @@ pub const RwLock = struct {
|
|||
|
||||
// At this point, we are in the writer_queue, so we might have already been resumed.
|
||||
|
||||
// We set this bit so that later we can rely on the fact, that if writer_queue_empty_bit is 1,
|
||||
// We set this bit so that later we can rely on the fact, that if writer_queue_empty == true,
|
||||
// some actor will attempt to grab the lock.
|
||||
@atomicStore(u8, &self.writer_queue_empty_bit, 0, .SeqCst);
|
||||
@atomicStore(bool, &self.writer_queue_empty, false, .SeqCst);
|
||||
|
||||
// Here we must be the one to acquire the write lock. It cannot already be locked.
|
||||
if (@cmpxchgStrong(State, &self.shared_state, .Unlocked, .WriteLock, .SeqCst, .SeqCst) == null) {
|
||||
|
|
@ -165,7 +165,7 @@ pub const RwLock = struct {
|
|||
// obtain the lock.
|
||||
// But if there's a writer_queue item or a reader_queue item,
|
||||
// we are the actor which must loop and attempt to grab the lock again.
|
||||
if (@atomicLoad(u8, &self.writer_queue_empty_bit, .SeqCst) == 0) {
|
||||
if (!@atomicLoad(bool, &self.writer_queue_empty, .SeqCst)) {
|
||||
if (@cmpxchgStrong(State, &self.shared_state, .Unlocked, .WriteLock, .SeqCst, .SeqCst) != null) {
|
||||
// We did not obtain the lock. Great, the queues are someone else's problem.
|
||||
return;
|
||||
|
|
@ -176,12 +176,12 @@ pub const RwLock = struct {
|
|||
return;
|
||||
}
|
||||
// Release the lock again.
|
||||
@atomicStore(u8, &self.writer_queue_empty_bit, 1, .SeqCst);
|
||||
@atomicStore(bool, &self.writer_queue_empty, true, .SeqCst);
|
||||
@atomicStore(State, &self.shared_state, .Unlocked, .SeqCst);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (@atomicLoad(u8, &self.reader_queue_empty_bit, .SeqCst) == 0) {
|
||||
if (!@atomicLoad(bool, &self.reader_queue_empty, .SeqCst)) {
|
||||
if (@cmpxchgStrong(State, &self.shared_state, .Unlocked, .ReadLock, .SeqCst, .SeqCst) != null) {
|
||||
// We did not obtain the lock. Great, the queues are someone else's problem.
|
||||
return;
|
||||
|
|
@ -195,7 +195,7 @@ pub const RwLock = struct {
|
|||
return;
|
||||
}
|
||||
// Release the lock again.
|
||||
@atomicStore(u8, &self.reader_queue_empty_bit, 1, .SeqCst);
|
||||
@atomicStore(bool, &self.reader_queue_empty, true, .SeqCst);
|
||||
if (@cmpxchgStrong(State, &self.shared_state, .ReadLock, .Unlocked, .SeqCst, .SeqCst) != null) {
|
||||
// Didn't unlock. Someone else's problem.
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -28397,15 +28397,15 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
|
|||
|
||||
if (operand_type->id == ZigTypeIdEnum && op != AtomicRmwOp_xchg) {
|
||||
ir_add_error(ira, &instruction->op->base,
|
||||
buf_sprintf("@atomicRmw on enum only works with .Xchg"));
|
||||
buf_sprintf("@atomicRmw with enum only allowed with .Xchg"));
|
||||
return ira->codegen->invalid_inst_gen;
|
||||
} else if (operand_type->id == ZigTypeIdBool && op != AtomicRmwOp_xchg) {
|
||||
ir_add_error(ira, &instruction->op->base,
|
||||
buf_sprintf("@atomicRmw on bool only works with .Xchg"));
|
||||
buf_sprintf("@atomicRmw with bool only allowed with .Xchg"));
|
||||
return ira->codegen->invalid_inst_gen;
|
||||
} else if (operand_type->id == ZigTypeIdFloat && op > AtomicRmwOp_sub) {
|
||||
ir_add_error(ira, &instruction->op->base,
|
||||
buf_sprintf("@atomicRmw with float only works with .Xchg, .Add and .Sub"));
|
||||
buf_sprintf("@atomicRmw with float only allowed with .Xchg, .Add and .Sub"));
|
||||
return ira->codegen->invalid_inst_gen;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,15 @@ const tests = @import("tests.zig");
|
|||
const std = @import("std");
|
||||
|
||||
pub fn addCases(cases: *tests.CompileErrorContext) void {
|
||||
cases.add("atomicrmw with bool op not .Xchg",
|
||||
\\export fn entry() void {
|
||||
\\ var x = false;
|
||||
\\ _ = @atomicRmw(bool, &x, .Add, true, .SeqCst);
|
||||
\\}
|
||||
, &[_][]const u8{
|
||||
"tmp.zig:3:30: error: @atomicRmw with bool only allowed with .Xchg",
|
||||
});
|
||||
|
||||
cases.addTest("combination of noasync and async",
|
||||
\\export fn entry() void {
|
||||
\\ noasync {
|
||||
|
|
@ -325,7 +334,7 @@ pub fn addCases(cases: *tests.CompileErrorContext) void {
|
|||
\\ _ = @atomicRmw(f32, &x, .And, 2, .SeqCst);
|
||||
\\}
|
||||
, &[_][]const u8{
|
||||
"tmp.zig:3:29: error: @atomicRmw with float only works with .Xchg, .Add and .Sub",
|
||||
"tmp.zig:3:29: error: @atomicRmw with float only allowed with .Xchg, .Add and .Sub",
|
||||
});
|
||||
|
||||
cases.add("intToPtr with misaligned address",
|
||||
|
|
@ -542,7 +551,7 @@ pub fn addCases(cases: *tests.CompileErrorContext) void {
|
|||
\\ _ = @atomicRmw(E, &x, .Add, .b, .SeqCst);
|
||||
\\}
|
||||
, &[_][]const u8{
|
||||
"tmp.zig:9:27: error: @atomicRmw on enum only works with .Xchg",
|
||||
"tmp.zig:9:27: error: @atomicRmw with enum only allowed with .Xchg",
|
||||
});
|
||||
|
||||
cases.add("disallow coercion from non-null-terminated pointer to null-terminated pointer",
|
||||
|
|
|
|||
Loading…
Reference in New Issue