Add more compiler-rt functions for ARM platform
parent
d3d77138ec
commit
e3a63b4e5a
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@ -75,6 +75,9 @@ comptime {
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@export("__floatsisf", @import("compiler_rt/floatsiXf.zig").__floatsisf, linkage);
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@export("__floatdidf", @import("compiler_rt/floatdidf.zig").__floatdidf, linkage);
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@export("__floatsitf", @import("compiler_rt/floatsiXf.zig").__floatsitf, linkage);
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@export("__floatunsisf", @import("compiler_rt/floatunsisf.zig").__floatunsisf, linkage);
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@export("__floatundisf", @import("compiler_rt/floatundisf.zig").__floatundisf, linkage);
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@export("__floatunsidf", @import("compiler_rt/floatunsidf.zig").__floatunsidf, linkage);
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@export("__floatundidf", @import("compiler_rt/floatundidf.zig").__floatundidf, linkage);
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@ -183,6 +186,8 @@ comptime {
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@export("__aeabi_l2d", @import("compiler_rt/floatdidf.zig").__floatdidf, linkage);
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@export("__aeabi_ui2d", @import("compiler_rt/floatunsidf.zig").__floatunsidf, linkage);
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@export("__aeabi_ul2d", @import("compiler_rt/floatundidf.zig").__floatundidf, linkage);
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@export("__aeabi_ui2f", @import("compiler_rt/floatunsisf.zig").__floatunsisf, linkage);
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@export("__aeabi_ul2f", @import("compiler_rt/floatundisf.zig").__floatundisf, linkage);
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@export("__aeabi_fneg", @import("compiler_rt/negXf2.zig").__negsf2, linkage);
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@export("__aeabi_dneg", @import("compiler_rt/negXf2.zig").__negdf2, linkage);
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@ -0,0 +1,86 @@
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const builtin = @import("builtin");
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const std = @import("std");
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const maxInt = std.math.maxInt;
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const FLT_MANT_DIG = 24;
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pub extern fn __floatundisf(arg: u64) f32 {
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@setRuntimeSafety(builtin.is_test);
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if (arg == 0) return 0;
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var a = arg;
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const N: usize = @TypeOf(a).bit_count;
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// Number of significant digits
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const sd = N - @clz(u64, a);
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// 8 exponent
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var e = @intCast(u32, sd) - 1;
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if (sd > FLT_MANT_DIG) {
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// start: 0000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQxxxxxxxxxxxxxxxxxx
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// finish: 000000000000000000000000000000000000001xxxxxxxxxxxxxxxxxxxxxxPQR
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// 12345678901234567890123456
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// 1 = msb 1 bit
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// P = bit FLT_MANT_DIG-1 bits to the right of 1
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// Q = bit FLT_MANT_DIG bits to the right of 1
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// R = "or" of all bits to the right of Q
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switch (sd) {
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FLT_MANT_DIG + 1 => a <<= 1,
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FLT_MANT_DIG + 2 => {},
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else => {
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const shift_amt = @intCast(u6, ((N + FLT_MANT_DIG + 2) - sd));
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const all_ones: u64 = maxInt(u64);
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a = (a >> @intCast(u6, sd - (FLT_MANT_DIG + 2))) |
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@boolToInt(a & (all_ones >> shift_amt) != 0);
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},
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}
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// Or P into R
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a |= @boolToInt((a & 4) != 0);
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// round - this step may add a significant bit
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a += 1;
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// dump Q and R
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a >>= 2;
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// a is now rounded to FLT_MANT_DIG or FLT_MANT_DIG+1 bits
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if ((a & (@as(u64, 1) << FLT_MANT_DIG)) != 0) {
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a >>= 1;
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e += 1;
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}
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// a is now rounded to FLT_MANT_DIG bits
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} else {
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a <<= @intCast(u6, FLT_MANT_DIG - sd);
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// a is now rounded to FLT_MANT_DIG bits
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}
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const result: u32 = ((e + 127) << 23) | // exponent
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@truncate(u32, a & 0x007FFFFF); // mantissa
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return @bitCast(f32, result);
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}
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fn test__floatundisf(a: u64, expected: f32) void {
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std.testing.expectEqual(expected, __floatundisf(a));
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}
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test "floatundisf" {
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test__floatundisf(0, 0.0);
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test__floatundisf(1, 1.0);
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test__floatundisf(2, 2.0);
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test__floatundisf(0x7FFFFF8000000000, 0x1.FFFFFEp+62F);
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test__floatundisf(0x7FFFFF0000000000, 0x1.FFFFFCp+62F);
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test__floatundisf(0x8000008000000000, 0x1p+63F);
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test__floatundisf(0x8000010000000000, 0x1.000002p+63F);
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test__floatundisf(0x8000000000000000, 0x1p+63F);
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test__floatundisf(0x8000000000000001, 0x1p+63F);
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test__floatundisf(0xFFFFFFFFFFFFFFFE, 0x1p+64F);
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test__floatundisf(0xFFFFFFFFFFFFFFFF, 0x1p+64F);
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test__floatundisf(0x0007FB72E8000000, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72EA000000, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72EB000000, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72EBFFFFFF, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72EC000000, 0x1.FEDCBCp+50F);
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test__floatundisf(0x0007FB72E8000001, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72E6000000, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72E7000000, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72E7FFFFFF, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72E4000001, 0x1.FEDCBAp+50F);
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test__floatundisf(0x0007FB72E4000000, 0x1.FEDCB8p+50F);
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}
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@ -0,0 +1,53 @@
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const builtin = @import("builtin");
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const std = @import("std");
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const maxInt = std.math.maxInt;
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const significandBits = 23;
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const exponentBias = 127;
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const implicitBit = @as(u32, 1) << significandBits;
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pub extern fn __floatunsisf(arg: u32) f32 {
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@setRuntimeSafety(builtin.is_test);
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if (arg == 0) return 0.0;
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// The exponent is the width of abs(a)
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const exp = @as(u32, 31) - @clz(u32, arg);
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var mantissa: u32 = undefined;
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if (exp <= significandBits) {
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// Shift a into the significand field and clear the implicit bit
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const shift = @intCast(u5, significandBits - exp);
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mantissa = @as(u32, arg) << shift ^ implicitBit;
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} else {
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const shift = @intCast(u5, exp - significandBits);
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// Round to the nearest number after truncation
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mantissa = @as(u32, arg) >> shift ^ implicitBit;
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// Align to the left and check if the truncated part is halfway over
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const round = arg << @intCast(u5, 31 - shift);
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mantissa += @boolToInt(round > 0x80000000);
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// Tie to even
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mantissa += mantissa & 1;
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}
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// Use the addition instead of a or since we may have a carry from the
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// mantissa to the exponent
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var result = mantissa;
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result += (exp + exponentBias) << significandBits;
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return @bitCast(f32, result);
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}
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fn test_one_floatunsisf(a: u32, expected: u32) void {
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const r = __floatunsisf(a);
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std.testing.expect(@bitCast(u32, r) == expected);
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}
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test "floatunsisf" {
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// Test the produced bit pattern
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test_one_floatunsisf(0, 0);
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test_one_floatunsisf(1, 0x3f800000);
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test_one_floatunsisf(0x7FFFFFFF, 0x4f000000);
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test_one_floatunsisf(0x80000000, 0x4f000000);
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test_one_floatunsisf(0xFFFFFFFF, 0x4f800000);
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}
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