Merge pull request #6255 from joachimschmidt557/stage2-arm
stage2 ARM: more instructions, return values, parametersmaster
Andrew Kelley
GitHub
commit
da596b7e4f
170
src/codegen.zig
170
src/codegen.zig
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@ -570,6 +570,39 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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try self.dbgSetEpilogueBegin();
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}
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},
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.arm => {
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const cc = self.fn_type.fnCallingConvention();
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if (cc != .Naked) {
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// push {fp, lr}
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// mov fp, sp
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// sub sp, sp, #reloc
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.push(.al, .{ .fp, .lr }).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .fp, Instruction.Operand.reg(.sp, Instruction.Operand.Shift.none)).toU32());
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// TODO: prepare stack for local variables
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// const backpatch_reloc = try self.code.addManyAsArray(4);
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try self.dbgSetPrologueEnd();
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try self.genBody(self.mod_fn.analysis.success);
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// Backpatch stack offset
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// const stack_end = self.max_end_stack;
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// const aligned_stack_end = mem.alignForward(stack_end, self.stack_align);
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// mem.writeIntLittle(u32, backpatch_reloc, Instruction.sub(.al, .sp, .sp, Instruction.Operand.imm()));
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try self.dbgSetEpilogueBegin();
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// mov sp, fp
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// pop {fp, pc}
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// TODO: return by jumping to this code, use relocations
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// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
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// mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.pop(.al, .{ .fp, .pc }).toU32());
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} else {
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try self.dbgSetPrologueEnd();
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try self.genBody(self.mod_fn.analysis.success);
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try self.dbgSetEpilogueBegin();
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}
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},
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else => {
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try self.dbgSetPrologueEnd();
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try self.genBody(self.mod_fn.analysis.success);
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@ -1461,7 +1494,35 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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}
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},
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.arm => {
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if (info.args.len > 0) return self.fail(inst.base.src, "TODO implement fn args for {}", .{self.target.cpu.arch});
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for (info.args) |mc_arg, arg_i| {
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const arg = inst.args[arg_i];
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const arg_mcv = try self.resolveInst(inst.args[arg_i]);
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switch (mc_arg) {
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.none => continue,
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.undef => unreachable,
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.immediate => unreachable,
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.unreach => unreachable,
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.dead => unreachable,
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.embedded_in_code => unreachable,
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.memory => unreachable,
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.compare_flags_signed => unreachable,
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.compare_flags_unsigned => unreachable,
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.register => |reg| {
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try self.genSetReg(arg.src, reg, arg_mcv);
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// TODO interact with the register allocator to mark the instruction as moved.
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},
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.stack_offset => {
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return self.fail(inst.base.src, "TODO implement calling with parameters in memory", .{});
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},
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.ptr_stack_offset => {
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return self.fail(inst.base.src, "TODO implement calling with MCValue.ptr_stack_offset arg", .{});
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},
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.ptr_embedded_in_code => {
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return self.fail(inst.base.src, "TODO implement calling with MCValue.ptr_embedded_in_code arg", .{});
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},
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}
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}
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if (inst.func.cast(ir.Inst.Constant)) |func_inst| {
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if (func_inst.val.cast(Value.Payload.Function)) |func_val| {
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@ -1476,13 +1537,16 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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else
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unreachable;
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// TODO only works with leaf functions
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// at the moment, which works fine for
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// Hello World, but not for real code
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// of course. Add pushing lr to stack
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// and popping after call
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try self.genSetReg(inst.base.src, .lr, .{ .memory = got_addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
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// TODO: add Instruction.supportedOn
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// function for ARM
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if (Target.arm.featureSetHas(self.target.cpu.features, .has_v5t)) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.blx(.al, .lr).toU32());
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} else {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .lr, Instruction.Operand.reg(.pc, Instruction.Operand.Shift.none)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
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}
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} else {
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return self.fail(inst.base.src, "TODO implement calling bitcasted functions", .{});
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}
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@ -1602,7 +1666,12 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.jalr(.zero, 0, .ra).toU32());
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},
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.arm => {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.bx(.al, .lr).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, .sp, Instruction.Operand.reg(.fp, Instruction.Operand.Shift.none)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.pop(.al, .{ .fp, .pc }).toU32());
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// TODO: jump to the end with relocation
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// // Just add space for an instruction, patch this later
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// try self.code.resize(self.code.items.len + 4);
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// try self.exitlude_jump_relocs.append(self.gpa, self.code.items.len - 4);
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},
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else => return self.fail(src, "TODO implement return for {}", .{self.target.cpu.arch}),
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}
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@ -2214,14 +2283,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// least amount of necessary instructions (use
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// more intelligent rotating)
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if (x <= math.maxInt(u8)) {
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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return;
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} else if (x <= math.maxInt(u16)) {
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// TODO Use movw Note: Not supported on
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// all ARM targets!
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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} else if (x <= math.maxInt(u32)) {
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// TODO Use movw and movt Note: Not
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// supported on all ARM targets! Also TODO
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@ -2233,20 +2302,28 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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// orr reg, reg, #0xbb, 24
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// orr reg, reg, #0xcc, 16
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// orr reg, reg, #0xdd, 8
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, 0, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, 0, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
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return;
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} else {
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return self.fail(src, "ARM registers are 32-bit wide", .{});
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}
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},
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.register => |src_reg| {
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// If the registers are the same, nothing to do.
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if (src_reg.id() == reg.id())
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return;
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// mov reg, src_reg
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.reg(src_reg, Instruction.Operand.Shift.none)).toU32());
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},
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.memory => |addr| {
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// The value is in memory at a hard-coded address.
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// If the type is a pointer, it means the pointer address is at this memory location.
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try self.genSetReg(src, reg, .{ .immediate = addr });
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, Instruction.Offset.none).toU32());
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mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.ldr(.al, reg, reg, .{ .offset = Instruction.Offset.none }).toU32());
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},
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else => return self.fail(src, "TODO implement getSetReg for arm {}", .{mcv}),
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},
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@ -2702,6 +2779,55 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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else => return self.fail(src, "TODO implement function parameters for {} on x86_64", .{cc}),
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}
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},
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.arm => {
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switch (cc) {
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.Naked => {
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assert(result.args.len == 0);
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result.return_value = .{ .unreach = {} };
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result.stack_byte_count = 0;
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result.stack_align = 1;
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return result;
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},
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.Unspecified, .C => {
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// ARM Procedure Call Standard, Chapter 6.5
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var ncrn: usize = 0; // Next Core Register Number
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var nsaa: u32 = 0; // Next stacked argument address
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for (param_types) |ty, i| {
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if (ty.abiAlignment(self.target.*) == 8) {
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// Round up NCRN to the next even number
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ncrn += ncrn % 2;
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}
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const param_size = @intCast(u32, ty.abiSize(self.target.*));
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if (std.math.divCeil(u32, param_size, 4) catch unreachable <= 4 - ncrn) {
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if (param_size <= 4) {
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result.args[i] = .{ .register = c_abi_int_param_regs[ncrn] };
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ncrn += 1;
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} else {
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return self.fail(src, "TODO MCValues with multiple registers", .{});
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}
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} else if (ncrn < 4 and nsaa == 0) {
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return self.fail(src, "TODO MCValues split between registers and stack", .{});
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} else {
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ncrn = 4;
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if (ty.abiAlignment(self.target.*) == 8) {
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if (nsaa % 8 != 0) {
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nsaa += 8 - (nsaa % 8);
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}
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}
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result.args[i] = .{ .stack_offset = nsaa };
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nsaa += param_size;
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}
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}
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result.stack_byte_count = nsaa;
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result.stack_align = 4;
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},
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else => return self.fail(src, "TODO implement function parameters for {} on arm", .{cc}),
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}
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},
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else => if (param_types.len != 0)
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return self.fail(src, "TODO implement codegen parameters for {}", .{self.target.cpu.arch}),
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}
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@ -2720,6 +2846,18 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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},
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else => return self.fail(src, "TODO implement function return values for {}", .{cc}),
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},
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.arm => switch (cc) {
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.Naked => unreachable,
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.Unspecified, .C => {
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const ret_ty_size = @intCast(u32, ret_ty.abiSize(self.target.*));
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if (ret_ty_size <= 4) {
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result.return_value = .{ .register = c_abi_int_return_regs[0] };
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} else {
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return self.fail(src, "TODO support more return types for ARM backend", .{});
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}
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},
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else => return self.fail(src, "TODO implement function return values for {}", .{cc}),
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},
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else => return self.fail(src, "TODO implement codegen return values for {}", .{self.target.cpu.arch}),
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}
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return result;
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@ -113,6 +113,13 @@ test "Register.id" {
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testing.expectEqual(@as(u4, 15), Register.pc.id());
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}
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/// Program status registers containing flags, mode bits and other
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/// vital information
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pub const Psr = enum {
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cpsr,
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spsr,
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};
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pub const callee_preserved_regs = [_]Register{ .r0, .r1, .r2, .r3, .r4, .r5, .r6, .r7, .r8, .r10 };
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pub const c_abi_int_param_regs = [_]Register{ .r0, .r1, .r2, .r3 };
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pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
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@ -135,15 +142,26 @@ pub const Instruction = union(enum) {
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offset: u12,
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rd: u4,
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rn: u4,
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l: u1,
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w: u1,
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b: u1,
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u: u1,
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p: u1,
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i: u1,
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load_store: u1,
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write_back: u1,
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byte_word: u1,
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up_down: u1,
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pre_post: u1,
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imm: u1,
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fixed: u2 = 0b01,
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cond: u4,
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},
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BlockDataTransfer: packed struct {
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register_list: u16,
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rn: u4,
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load_store: u1,
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write_back: u1,
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psr_or_user: u1,
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up_down: u1,
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pre_post: u1,
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fixed: u3 = 0b100,
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cond: u4,
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},
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Branch: packed struct {
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offset: u24,
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link: u1,
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@ -235,14 +253,14 @@ pub const Instruction = union(enum) {
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rs: u4,
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},
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const Type = enum(u2) {
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LogicalLeft,
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LogicalRight,
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ArithmeticRight,
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RotateRight,
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pub const Type = enum(u2) {
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logical_left,
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logical_right,
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arithmetic_right,
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rotate_right,
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};
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const none = Shift{
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pub const none = Shift{
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.Immediate = .{
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.amount = 0,
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.typ = 0,
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@ -338,10 +356,32 @@ pub const Instruction = union(enum) {
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}
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};
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/// Represents the register list operand to a block data transfer
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/// instruction
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pub const RegisterList = packed struct {
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r0: bool = false,
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r1: bool = false,
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r2: bool = false,
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r3: bool = false,
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r4: bool = false,
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r5: bool = false,
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r6: bool = false,
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r7: bool = false,
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r8: bool = false,
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r9: bool = false,
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r10: bool = false,
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r11: bool = false,
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r12: bool = false,
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r13: bool = false,
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r14: bool = false,
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r15: bool = false,
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};
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pub fn toU32(self: Instruction) u32 {
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return switch (self) {
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.DataProcessing => |v| @bitCast(u32, v),
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.SingleDataTransfer => |v| @bitCast(u32, v),
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.BlockDataTransfer => |v| @bitCast(u32, v),
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.Branch => |v| @bitCast(u32, v),
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.BranchExchange => |v| @bitCast(u32, v),
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.SupervisorCall => |v| @bitCast(u32, v),
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@ -362,7 +402,7 @@ pub const Instruction = union(enum) {
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return Instruction{
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.DataProcessing = .{
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.cond = @enumToInt(cond),
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.i = if (op2 == .Immediate) 1 else 0,
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.i = @boolToInt(op2 == .Immediate),
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.opcode = @enumToInt(opcode),
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.s = s,
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.rn = rn.id(),
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@ -377,10 +417,10 @@ pub const Instruction = union(enum) {
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rd: Register,
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rn: Register,
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offset: Offset,
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pre_post: u1,
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up_down: u1,
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pre_index: bool,
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positive: bool,
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byte_word: u1,
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writeback: u1,
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write_back: bool,
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load_store: u1,
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) Instruction {
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return Instruction{
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@ -389,12 +429,36 @@ pub const Instruction = union(enum) {
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.rn = rn.id(),
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.rd = rd.id(),
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.offset = offset.toU12(),
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.l = load_store,
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.w = writeback,
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.b = byte_word,
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.u = up_down,
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.p = pre_post,
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.i = if (offset == .Immediate) 0 else 1,
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.load_store = load_store,
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.write_back = @boolToInt(write_back),
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.byte_word = byte_word,
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.up_down = @boolToInt(positive),
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.pre_post = @boolToInt(pre_index),
|
||||
.imm = @boolToInt(offset != .Immediate),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
fn blockDataTransfer(
|
||||
cond: Condition,
|
||||
rn: Register,
|
||||
reg_list: RegisterList,
|
||||
pre_post: u1,
|
||||
up_down: u1,
|
||||
psr_or_user: u1,
|
||||
write_back: bool,
|
||||
load_store: u1,
|
||||
) Instruction {
|
||||
return Instruction{
|
||||
.BlockDataTransfer = .{
|
||||
.register_list = @bitCast(u16, reg_list),
|
||||
.rn = rn.id(),
|
||||
.load_store = load_store,
|
||||
.write_back = @boolToInt(write_back),
|
||||
.psr_or_user = psr_or_user,
|
||||
.up_down = up_down,
|
||||
.pre_post = pre_post,
|
||||
.cond = @enumToInt(cond),
|
||||
},
|
||||
};
|
||||
}
|
||||
|
|
@ -442,36 +506,68 @@ pub const Instruction = union(enum) {
|
|||
|
||||
// Data processing
|
||||
|
||||
pub fn @"and"(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .@"and", s, rd, rn, op2);
|
||||
pub fn @"and"(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .@"and", 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn eor(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .eor, s, rd, rn, op2);
|
||||
pub fn ands(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .@"and", 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sub(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sub, s, rd, rn, op2);
|
||||
pub fn eor(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .eor, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rsb(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsb, s, rd, rn, op2);
|
||||
pub fn eors(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .eor, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn add(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .add, s, rd, rn, op2);
|
||||
pub fn sub(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sub, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn adc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .adc, s, rd, rn, op2);
|
||||
pub fn subs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sub, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sbc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sbc, s, rd, rn, op2);
|
||||
pub fn rsb(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsb, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rsc(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsc, s, rd, rn, op2);
|
||||
pub fn rsbs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsb, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn add(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .add, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn adds(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .add, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn adc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .adc, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn adcs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .adc, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sbc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sbc, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn sbcs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .sbc, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rsc(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsc, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn rscs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .rsc, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn tst(cond: Condition, rn: Register, op2: Operand) Instruction {
|
||||
|
|
@ -490,32 +586,115 @@ pub const Instruction = union(enum) {
|
|||
return dataProcessing(cond, .cmn, 1, .r0, rn, op2);
|
||||
}
|
||||
|
||||
pub fn orr(cond: Condition, s: u1, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, s, rd, rn, op2);
|
||||
pub fn orr(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn mov(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, s, rd, .r0, op2);
|
||||
pub fn orrs(cond: Condition, rd: Register, rn: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .orr, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn bic(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, s, rd, rn, op2);
|
||||
pub fn mov(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, 0, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn mvn(cond: Condition, s: u1, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, s, rd, .r0, op2);
|
||||
pub fn movs(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mov, 1, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn bic(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, 0, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn bics(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .bic, 1, rd, rn, op2);
|
||||
}
|
||||
|
||||
pub fn mvn(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, 0, rd, .r0, op2);
|
||||
}
|
||||
|
||||
pub fn mvns(cond: Condition, rd: Register, op2: Operand) Instruction {
|
||||
return dataProcessing(cond, .mvn, 1, rd, .r0, op2);
|
||||
}
|
||||
|
||||
// PSR transfer
|
||||
|
||||
pub fn mrs(cond: Condition, rd: Register, psr: Psr) Instruction {
|
||||
return dataProcessing(cond, if (psr == .cpsr) .tst else .cmp, 0, rd, .r15, Operand.reg(.r0, Operand.Shift.none));
|
||||
}
|
||||
|
||||
// Single data transfer
|
||||
|
||||
pub fn ldr(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 1);
|
||||
pub const OffsetArgs = struct {
|
||||
pre_index: bool = true,
|
||||
positive: bool = true,
|
||||
offset: Offset,
|
||||
write_back: bool = false,
|
||||
};
|
||||
|
||||
pub fn ldr(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 0, args.write_back, 1);
|
||||
}
|
||||
|
||||
pub fn str(cond: Condition, rd: Register, rn: Register, offset: Offset) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, offset, 1, 1, 0, 0, 0);
|
||||
pub fn ldrb(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 1);
|
||||
}
|
||||
|
||||
pub fn str(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 0, args.write_back, 0);
|
||||
}
|
||||
|
||||
pub fn strb(cond: Condition, rd: Register, rn: Register, args: OffsetArgs) Instruction {
|
||||
return singleDataTransfer(cond, rd, rn, args.offset, args.pre_index, args.positive, 1, args.write_back, 0);
|
||||
}
|
||||
|
||||
// Block data transfer
|
||||
|
||||
pub fn ldmda(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 0, 0, 0, write_back, 1);
|
||||
}
|
||||
|
||||
pub fn ldmdb(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 1, 0, 0, write_back, 1);
|
||||
}
|
||||
|
||||
pub fn ldmib(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 1, 1, 0, write_back, 1);
|
||||
}
|
||||
|
||||
pub fn ldmia(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 0, 1, 0, write_back, 1);
|
||||
}
|
||||
|
||||
pub const ldmfa = ldmda;
|
||||
pub const ldmea = ldmdb;
|
||||
pub const ldmed = ldmib;
|
||||
pub const ldmfd = ldmia;
|
||||
pub const ldm = ldmia;
|
||||
|
||||
pub fn stmda(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 0, 0, 0, write_back, 0);
|
||||
}
|
||||
|
||||
pub fn stmdb(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 1, 0, 0, write_back, 0);
|
||||
}
|
||||
|
||||
pub fn stmib(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 1, 1, 0, write_back, 0);
|
||||
}
|
||||
|
||||
pub fn stmia(cond: Condition, rn: Register, write_back: bool, reg_list: RegisterList) Instruction {
|
||||
return blockDataTransfer(cond, rn, reg_list, 0, 1, 0, write_back, 0);
|
||||
}
|
||||
|
||||
pub const stmed = stmda;
|
||||
pub const stmfd = stmdb;
|
||||
pub const stmfa = stmib;
|
||||
pub const stmea = stmia;
|
||||
pub const stm = stmia;
|
||||
|
||||
// Branch
|
||||
|
||||
pub fn b(cond: Condition, offset: i24) Instruction {
|
||||
|
|
@ -549,6 +728,58 @@ pub const Instruction = union(enum) {
|
|||
pub fn bkpt(imm: u16) Instruction {
|
||||
return breakpoint(imm);
|
||||
}
|
||||
|
||||
// Aliases
|
||||
|
||||
pub fn pop(cond: Condition, args: anytype) Instruction {
|
||||
if (@typeInfo(@TypeOf(args)) != .Struct) {
|
||||
@compileError("Expected tuple or struct argument, found " ++ @typeName(@TypeOf(args)));
|
||||
}
|
||||
|
||||
if (args.len < 1) {
|
||||
@compileError("Expected at least one register");
|
||||
} else if (args.len == 1) {
|
||||
const reg = args[0];
|
||||
return ldr(cond, reg, .sp, .{
|
||||
.pre_index = false,
|
||||
.positive = true,
|
||||
.offset = Offset.imm(4),
|
||||
.write_back = false,
|
||||
});
|
||||
} else {
|
||||
var register_list: u16 = 0;
|
||||
inline for (args) |arg| {
|
||||
const reg = @as(Register, arg);
|
||||
register_list |= @as(u16, 1) << reg.id();
|
||||
}
|
||||
return ldm(cond, .sp, true, @bitCast(RegisterList, register_list));
|
||||
}
|
||||
}
|
||||
|
||||
pub fn push(cond: Condition, args: anytype) Instruction {
|
||||
if (@typeInfo(@TypeOf(args)) != .Struct) {
|
||||
@compileError("Expected tuple or struct argument, found " ++ @typeName(@TypeOf(args)));
|
||||
}
|
||||
|
||||
if (args.len < 1) {
|
||||
@compileError("Expected at least one register");
|
||||
} else if (args.len == 1) {
|
||||
const reg = args[0];
|
||||
return str(cond, reg, .sp, .{
|
||||
.pre_index = true,
|
||||
.positive = false,
|
||||
.offset = Offset.imm(4),
|
||||
.write_back = true,
|
||||
});
|
||||
} else {
|
||||
var register_list: u16 = 0;
|
||||
inline for (args) |arg| {
|
||||
const reg = @as(Register, arg);
|
||||
register_list |= @as(u16, 1) << reg.id();
|
||||
}
|
||||
return stmdb(cond, .sp, true, @bitCast(RegisterList, register_list));
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
test "serialize instructions" {
|
||||
|
|
@ -559,23 +790,31 @@ test "serialize instructions" {
|
|||
|
||||
const testcases = [_]Testcase{
|
||||
.{ // add r0, r0, r0
|
||||
.inst = Instruction.add(.al, 0, .r0, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none)),
|
||||
.inst = Instruction.add(.al, .r0, .r0, Instruction.Operand.reg(.r0, Instruction.Operand.Shift.none)),
|
||||
.expected = 0b1110_00_0_0100_0_0000_0000_00000000_0000,
|
||||
},
|
||||
.{ // mov r4, r2
|
||||
.inst = Instruction.mov(.al, 0, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
|
||||
.inst = Instruction.mov(.al, .r4, Instruction.Operand.reg(.r2, Instruction.Operand.Shift.none)),
|
||||
.expected = 0b1110_00_0_1101_0_0000_0100_00000000_0010,
|
||||
},
|
||||
.{ // mov r0, #42
|
||||
.inst = Instruction.mov(.al, 0, .r0, Instruction.Operand.imm(42, 0)),
|
||||
.inst = Instruction.mov(.al, .r0, Instruction.Operand.imm(42, 0)),
|
||||
.expected = 0b1110_00_1_1101_0_0000_0000_0000_00101010,
|
||||
},
|
||||
.{ // mrs r5, cpsr
|
||||
.inst = Instruction.mrs(.al, .r5, .cpsr),
|
||||
.expected = 0b1110_00010_0_001111_0101_000000000000,
|
||||
},
|
||||
.{ // ldr r0, [r2, #42]
|
||||
.inst = Instruction.ldr(.al, .r0, .r2, Instruction.Offset.imm(42)),
|
||||
.inst = Instruction.ldr(.al, .r0, .r2, .{
|
||||
.offset = Instruction.Offset.imm(42),
|
||||
}),
|
||||
.expected = 0b1110_01_0_1_1_0_0_1_0010_0000_000000101010,
|
||||
},
|
||||
.{ // str r0, [r3]
|
||||
.inst = Instruction.str(.al, .r0, .r3, Instruction.Offset.none),
|
||||
.inst = Instruction.str(.al, .r0, .r3, .{
|
||||
.offset = Instruction.Offset.none,
|
||||
}),
|
||||
.expected = 0b1110_01_0_1_1_0_0_0_0011_0000_000000000000,
|
||||
},
|
||||
.{ // b #12
|
||||
|
|
@ -598,6 +837,14 @@ test "serialize instructions" {
|
|||
.inst = Instruction.bkpt(42),
|
||||
.expected = 0b1110_0001_0010_000000000010_0111_1010,
|
||||
},
|
||||
.{ // stmdb r9, {r0}
|
||||
.inst = Instruction.stmdb(.al, .r9, false, .{ .r0 = true }),
|
||||
.expected = 0b1110_100_1_0_0_0_0_1001_0000000000000001,
|
||||
},
|
||||
.{ // ldmea r4!, {r2, r5}
|
||||
.inst = Instruction.ldmea(.al, .r4, true, .{ .r2 = true, .r5 = true }),
|
||||
.expected = 0b1110_100_1_0_0_1_1_0100_0000000000100100,
|
||||
},
|
||||
};
|
||||
|
||||
for (testcases) |case| {
|
||||
|
|
@ -605,3 +852,43 @@ test "serialize instructions" {
|
|||
testing.expectEqual(case.expected, actual);
|
||||
}
|
||||
}
|
||||
|
||||
test "aliases" {
|
||||
const Testcase = struct {
|
||||
expected: Instruction,
|
||||
actual: Instruction,
|
||||
};
|
||||
|
||||
const testcases = [_]Testcase{
|
||||
.{ // pop { r6 }
|
||||
.actual = Instruction.pop(.al, .{.r6}),
|
||||
.expected = Instruction.ldr(.al, .r6, .sp, .{
|
||||
.pre_index = false,
|
||||
.positive = true,
|
||||
.offset = Instruction.Offset.imm(4),
|
||||
.write_back = false,
|
||||
}),
|
||||
},
|
||||
.{ // pop { r1, r5 }
|
||||
.actual = Instruction.pop(.al, .{ .r1, .r5 }),
|
||||
.expected = Instruction.ldm(.al, .sp, true, .{ .r1 = true, .r5 = true }),
|
||||
},
|
||||
.{ // push { r3 }
|
||||
.actual = Instruction.push(.al, .{.r3}),
|
||||
.expected = Instruction.str(.al, .r3, .sp, .{
|
||||
.pre_index = true,
|
||||
.positive = false,
|
||||
.offset = Instruction.Offset.imm(4),
|
||||
.write_back = true,
|
||||
}),
|
||||
},
|
||||
.{ // push { r0, r2 }
|
||||
.actual = Instruction.push(.al, .{ .r0, .r2 }),
|
||||
.expected = Instruction.stmdb(.al, .sp, true, .{ .r0 = true, .r2 = true }),
|
||||
},
|
||||
};
|
||||
|
||||
for (testcases) |case| {
|
||||
testing.expectEqual(case.expected.toU32(), case.actual.toU32());
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,116 @@
|
|||
const std = @import("std");
|
||||
const TestContext = @import("../../src/test.zig").TestContext;
|
||||
|
||||
const linux_arm = std.zig.CrossTarget{
|
||||
.cpu_arch = .arm,
|
||||
.os_tag = .linux,
|
||||
};
|
||||
|
||||
pub fn addCases(ctx: *TestContext) !void {
|
||||
{
|
||||
var case = ctx.exe("hello world", linux_arm);
|
||||
// Regular old hello world
|
||||
case.addCompareOutput(
|
||||
\\export fn _start() noreturn {
|
||||
\\ print();
|
||||
\\ exit();
|
||||
\\}
|
||||
\\
|
||||
\\fn print() void {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (4),
|
||||
\\ [arg1] "{r0}" (1),
|
||||
\\ [arg2] "{r1}" (@ptrToInt("Hello, World!\n")),
|
||||
\\ [arg3] "{r2}" (14)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ return;
|
||||
\\}
|
||||
\\
|
||||
\\fn exit() noreturn {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (1),
|
||||
\\ [arg1] "{r0}" (0)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("parameters and return values", linux_arm);
|
||||
// Testing simple parameters and return values
|
||||
//
|
||||
// TODO: The parameters to the asm statement in print() had to
|
||||
// be in a specific order because otherwise the write to r0
|
||||
// would overwrite the len parameter which resides in r0
|
||||
case.addCompareOutput(
|
||||
\\export fn _start() noreturn {
|
||||
\\ print(id(14));
|
||||
\\ exit();
|
||||
\\}
|
||||
\\
|
||||
\\fn id(x: u32) u32 {
|
||||
\\ return x;
|
||||
\\}
|
||||
\\
|
||||
\\fn print(len: u32) void {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (4),
|
||||
\\ [arg3] "{r2}" (len),
|
||||
\\ [arg1] "{r0}" (1),
|
||||
\\ [arg2] "{r1}" (@ptrToInt("Hello, World!\n"))
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ return;
|
||||
\\}
|
||||
\\
|
||||
\\fn exit() noreturn {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (1),
|
||||
\\ [arg1] "{r0}" (0)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("non-leaf functions", linux_arm);
|
||||
// Testing non-leaf functions
|
||||
case.addCompareOutput(
|
||||
\\export fn _start() noreturn {
|
||||
\\ foo();
|
||||
\\ exit();
|
||||
\\}
|
||||
\\
|
||||
\\fn foo() void {
|
||||
\\ bar();
|
||||
\\}
|
||||
\\
|
||||
\\fn bar() void {}
|
||||
\\
|
||||
\\fn exit() noreturn {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (1),
|
||||
\\ [arg1] "{r0}" (0)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
"",
|
||||
);
|
||||
}
|
||||
}
|
||||
|
|
@ -21,11 +21,6 @@ const linux_riscv64 = std.zig.CrossTarget{
|
|||
.os_tag = .linux,
|
||||
};
|
||||
|
||||
const linux_arm = std.zig.CrossTarget{
|
||||
.cpu_arch = .arm,
|
||||
.os_tag = .linux,
|
||||
};
|
||||
|
||||
const wasi = std.zig.CrossTarget{
|
||||
.cpu_arch = .wasm32,
|
||||
.os_tag = .wasi,
|
||||
|
|
@ -35,6 +30,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
try @import("zir.zig").addCases(ctx);
|
||||
try @import("cbe.zig").addCases(ctx);
|
||||
try @import("spu-ii.zig").addCases(ctx);
|
||||
try @import("arm.zig").addCases(ctx);
|
||||
|
||||
{
|
||||
var case = ctx.exe("hello world with updates", linux_x64);
|
||||
|
|
@ -76,7 +72,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
// Now change the message only
|
||||
|
|
@ -108,7 +104,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"What is up? This is a longer message that will force the data to be relocated in virtual address space.\n",
|
||||
);
|
||||
// Now we print it twice.
|
||||
|
|
@ -223,42 +219,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
var case = ctx.exe("hello world", linux_arm);
|
||||
// Regular old hello world
|
||||
case.addCompareOutput(
|
||||
\\export fn _start() noreturn {
|
||||
\\ print();
|
||||
\\ exit();
|
||||
\\}
|
||||
\\
|
||||
\\fn print() void {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (4),
|
||||
\\ [arg1] "{r0}" (1),
|
||||
\\ [arg2] "{r1}" (@ptrToInt("Hello, World!\n")),
|
||||
\\ [arg3] "{r2}" (14)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ return;
|
||||
\\}
|
||||
\\
|
||||
\\fn exit() noreturn {
|
||||
\\ asm volatile ("svc #0"
|
||||
\\ :
|
||||
\\ : [number] "{r7}" (1),
|
||||
\\ [arg1] "{r0}" (0)
|
||||
\\ : "memory"
|
||||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
|
|
@ -283,7 +244,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"Hello, World!\n",
|
||||
);
|
||||
}
|
||||
|
|
@ -310,7 +271,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
}
|
||||
|
|
@ -337,7 +298,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
}
|
||||
|
|
@ -368,7 +329,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -401,7 +362,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -437,7 +398,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -474,7 +435,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -504,7 +465,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -538,7 +499,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -562,7 +523,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -601,7 +562,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"hello\nhello\nhello\nhello\n",
|
||||
);
|
||||
|
||||
|
|
@ -638,7 +599,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -680,7 +641,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -732,7 +693,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -794,7 +755,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -827,7 +788,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -859,7 +820,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -884,7 +845,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -910,7 +871,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"",
|
||||
);
|
||||
|
||||
|
|
@ -943,7 +904,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ );
|
||||
\\ unreachable;
|
||||
\\}
|
||||
,
|
||||
,
|
||||
"hello\nhello\nhello\nhello\nhello\n",
|
||||
);
|
||||
}
|
||||
|
|
@ -1000,7 +961,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ bar();
|
||||
\\}
|
||||
\\fn bar() void {}
|
||||
,
|
||||
,
|
||||
"42\n",
|
||||
);
|
||||
|
||||
|
|
@ -1018,7 +979,7 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ bar();
|
||||
\\}
|
||||
\\fn bar() void {}
|
||||
,
|
||||
,
|
||||
"42\n",
|
||||
);
|
||||
|
||||
|
|
@ -1034,10 +995,10 @@ pub fn addCases(ctx: *TestContext) !void {
|
|||
\\ bar();
|
||||
\\}
|
||||
\\fn bar() void {}
|
||||
,
|
||||
// This is what you get when you take the bits of the IEE-754
|
||||
// representation of 42.0 and reinterpret them as an unsigned
|
||||
// integer. Guess that's a bug in wasmtime.
|
||||
,
|
||||
// This is what you get when you take the bits of the IEE-754
|
||||
// representation of 42.0 and reinterpret them as an unsigned
|
||||
// integer. Guess that's a bug in wasmtime.
|
||||
"1109917696\n",
|
||||
);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue