riscv musl: only add the +a feature
parent
d4ca337e6b
commit
afbf99c846
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@ -8409,16 +8409,11 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa
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if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) {
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if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) {
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// Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's
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// Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's
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// cross compilation CPU info for RISCV.
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// cross compilation CPU info for RISCV.
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switch (g->zig_target->arch) {
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// TODO: https://github.com/ziglang/zig/issues/2883
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case ZigLLVM_riscv32:
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args.append("-Xclang");
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args.append("-march=rv32ia");
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args.append("-target-feature");
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break;
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args.append("-Xclang");
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case ZigLLVM_riscv64:
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args.append("+a");
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args.append("-march=rv64ia");
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break;
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default:
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zig_unreachable();
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}
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}
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}
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}
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}
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if (g->zig_target->os == OsFreestanding) {
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if (g->zig_target->os == OsFreestanding) {
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