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riscv musl: only add the +a feature

master
Andrew Kelley 2019-07-18 12:28:24 -04:00
parent d4ca337e6b
commit afbf99c846
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GPG Key ID: 7C5F548F728501A9
1 changed files with 5 additions and 10 deletions
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15
src/codegen.cpp
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@ -8409,16 +8409,11 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa
if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) { if (target_is_musl(g->zig_target) && target_is_riscv(g->zig_target)) {
// Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's // Musl depends on atomic instructions, which are disabled by default in Clang/LLVM's
// cross compilation CPU info for RISCV. // cross compilation CPU info for RISCV.
switch (g->zig_target->arch) { // TODO: https://github.com/ziglang/zig/issues/2883
case ZigLLVM_riscv32: args.append("-Xclang");
args.append("-march=rv32ia"); args.append("-target-feature");
break; args.append("-Xclang");
case ZigLLVM_riscv64: args.append("+a");
args.append("-march=rv64ia");
break;
default:
zig_unreachable();
}
} }
} }
if (g->zig_target->os == OsFreestanding) { if (g->zig_target->os == OsFreestanding) {