stage2: starting on a riscv64 backend
pfg
Andrew Kelley
parent
952a397b0e
commit
52ae2b10aa
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@ -78,7 +78,7 @@ pub fn generateSymbol(
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//.r600 => return Function(.r600).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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//.amdgcn => return Function(.amdgcn).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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//.riscv32 => return Function(.riscv32).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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//.riscv64 => return Function(.riscv64).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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.riscv64 => return Function(.riscv64).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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//.sparc => return Function(.sparc).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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//.sparcv9 => return Function(.sparcv9).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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//.sparcel => return Function(.sparcel).generateSymbol(bin_file, src, typed_value, code, dbg_line),
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@ -1023,6 +1023,14 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.i386, .x86_64 => {
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try self.code.append(0xcc); // int3
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},
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.riscv64 => {
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const full = @bitCast(u32, Instructions.CallBreak{
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.mode = @enumToInt(Instructions.CallBreak.Mode.ebreak),
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});
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try self.code.resize(self.code.items.len + 4);
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mem.writeIntLittle(u32, self.code.items[self.code.items.len - 4 ..][0..4], full);
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},
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else => return self.fail(src, "TODO implement @breakpoint() for {}", .{self.target.cpu.arch}),
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}
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return .none;
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@ -1325,9 +1333,43 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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fn genAsm(self: *Self, inst: *ir.Inst.Assembly) !MCValue {
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if (!inst.is_volatile and inst.base.isUnused())
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return MCValue.dead;
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if (arch != .x86_64 and arch != .i386) {
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return self.fail(inst.base.src, "TODO implement inline asm support for more architectures", .{});
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switch (arch) {
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.riscv64 => {
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for (inst.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input});
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}
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const reg_name = input[1 .. input.len - 1];
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const reg = parseRegName(reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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const arg = try self.resolveInst(inst.args[i]);
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try self.genSetReg(inst.base.src, reg, arg);
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}
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if (mem.eql(u8, inst.asm_source, "ecall")) {
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const full = @bitCast(u32, Instructions.CallBreak{
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.mode = @enumToInt(Instructions.CallBreak.Mode.ecall),
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});
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try self.code.resize(self.code.items.len + 4);
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mem.writeIntLittle(u32, self.code.items[self.code.items.len - 4 ..][0..4], full);
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} else {
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return self.fail(inst.base.src, "TODO implement support for more riscv64 assembly instructions", .{});
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}
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if (inst.output) |output| {
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if (output.len < 4 or output[0] != '=' or output[1] != '{' or output[output.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm output constraint: '{}'", .{output});
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}
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const reg_name = output[2 .. output.len - 1];
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const reg = parseRegName(reg_name) orelse
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return self.fail(inst.base.src, "unrecognized register: '{}'", .{reg_name});
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return MCValue{ .register = reg };
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} else {
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return MCValue.none;
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}
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},
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.x86_64, .i386 => {
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for (inst.inputs) |input, i| {
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if (input.len < 3 or input[0] != '{' or input[input.len - 1] != '}') {
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return self.fail(inst.base.src, "unrecognized asm input constraint: '{}'", .{input});
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@ -1356,6 +1398,9 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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} else {
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return MCValue.none;
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}
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},
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else => return self.fail(inst.base.src, "TODO implement inline asm support for more architectures", .{}),
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}
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}
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/// Encodes a REX prefix as specified, and appends it to the instruction
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@ -1500,6 +1545,31 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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fn genSetReg(self: *Self, src: usize, reg: Register, mcv: MCValue) InnerError!void {
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switch (arch) {
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.riscv64 => switch (mcv) {
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.immediate => |x| {
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if (x > math.maxInt(u11)) {
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return self.fail(src, "TODO genSetReg 12+ bit immediates for riscv64", .{});
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}
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const Instruction = packed struct {
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opcode: u7,
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rd: u5,
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mode: u3,
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rsi1: u5,
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imm: u11,
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signextend: u1 = 0,
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};
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const full = @bitCast(u32, Instructions.Addi{
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.imm = @intCast(u11, x),
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.rsi1 = Register.zero.id(),
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.mode = @enumToInt(Instructions.Addi.Mode.addi),
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.rd = reg.id(),
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});
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try self.code.resize(self.code.items.len + 4);
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mem.writeIntLittle(u32, self.code.items[self.code.items.len - 4 ..][0..4], full);
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},
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else => return self.fail(src, "TODO implement getSetReg for riscv64 MCValue {}", .{mcv}),
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},
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.x86_64 => switch (mcv) {
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.dead => unreachable,
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.ptr_stack_offset => unreachable,
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@ -1873,7 +1943,8 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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else => return self.fail(src, "TODO implement function parameters for {}", .{cc}),
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}
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},
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else => return self.fail(src, "TODO implement codegen parameters for {}", .{self.target.cpu.arch}),
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else => if (param_types.len != 0)
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return self.fail(src, "TODO implement codegen parameters for {}", .{self.target.cpu.arch}),
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}
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if (ret_ty.zigTypeTag() == .NoReturn) {
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@ -1915,6 +1986,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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usingnamespace switch (arch) {
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.i386 => @import("codegen/x86.zig"),
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.x86_64 => @import("codegen/x86_64.zig"),
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.riscv64 => @import("codegen/riscv64.zig"),
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else => struct {
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pub const Register = enum {
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dummy,
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@ -0,0 +1,68 @@
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pub const Instructions = struct {
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pub const CallBreak = packed struct {
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pub const Mode = packed enum(u12) { ecall, ebreak };
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opcode: u7 = 0b1110011,
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unused1: u5 = 0,
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unused2: u3 = 0,
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unused3: u5 = 0,
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mode: u12,
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};
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pub const Addi = packed struct {
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pub const Mode = packed enum(u3) { addi = 0b000, slti = 0b010, sltiu = 0b011, xori = 0b100, ori = 0b110, andi = 0b111 };
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opcode: u7 = 0b0010011,
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rd: u5,
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mode: u3,
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rsi1: u5,
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imm: u11,
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signextend: u1 = 0,
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};
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};
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// zig fmt: off
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pub const Register = enum(u8) {
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// 64 bit registers
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zero = 0, // zero
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ra = 1, // return address. caller saved
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sp = 2, // stack pointer. callee saved.
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gp = 3, // global pointer
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tp = 4, // thread pointer
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t0 = 5, t1 = 6, t2 = 7, // temporaries. caller saved.
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s0 = 8, // s0/fp, callee saved.
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s1, // callee saved.
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a0, a1, // fn args/return values. caller saved.
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a2, a3, a4, a5, a6, a7, // fn args. caller saved.
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s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, // saved registers. callee saved.
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t3, t4, t5, t6, // caller saved
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/// Returns the bit-width of the register.
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pub fn size(self: @This()) u7 {
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return switch (@enumToInt(self)) {
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0...31 => 64,
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else => unreachable,
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};
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}
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pub fn to64(self: @This()) Register {
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return self;
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}
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/// Returns the register's id. This is used in practically every opcode the
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/// riscv64 has.
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pub fn id(self: @This()) u5 {
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return @truncate(u5, @enumToInt(self));
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}
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/// Returns the index into `callee_preserved_regs`.
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pub fn allocIndex(self: Register) ?u4 {
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inline for(callee_preserved_regs) |cpreg, i| {
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if(self == cpreg) return i;
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}
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return null;
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}
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};
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// zig fmt: on
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pub const callee_preserved_regs = [_]Register{
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.s0, .s1, .s2, .s3, .s4, .s5, .s6, .s7, .s8, .s9, .s10, .s11,
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};
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@ -7,6 +7,11 @@ const linux_x64 = std.zig.CrossTarget{
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.os_tag = .linux,
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};
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const riscv64 = std.zig.CrossTarget{
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.cpu_arch = .riscv64,
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.os_tag = .linux,
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};
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pub fn addCases(ctx: *TestContext) !void {
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if (std.Target.current.os.tag != .linux or
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std.Target.current.cpu.arch != .x86_64)
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