compiler-rt: Add __divmodsi4, __aeabi_idivmod
parent
738562e990
commit
4e241263ff
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@ -106,6 +106,7 @@ comptime {
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@export("__udivsi3", __udivsi3, linkage);
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@export("__udivdi3", __udivdi3, linkage);
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@export("__umoddi3", __umoddi3, linkage);
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@export("__divmodsi4", __divmodsi4, linkage);
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@export("__udivmodsi4", __udivmodsi4, linkage);
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@export("__negsf2", @import("compiler_rt/negXf2.zig").__negsf2, linkage);
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@ -113,10 +114,11 @@ comptime {
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if (is_arm_arch and !is_arm_64) {
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@export("__aeabi_uldivmod", __aeabi_uldivmod, linkage);
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@export("__aeabi_uidivmod", __aeabi_uidivmod, linkage);
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@export("__aeabi_idiv", __divsi3, linkage);
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@export("__aeabi_idivmod", __divmodsi4, linkage);
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@export("__aeabi_uidiv", __udivsi3, linkage);
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@export("__aeabi_uidivmod", __aeabi_uidivmod, linkage);
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@export("__aeabi_memcpy", __aeabi_memcpy, linkage);
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@export("__aeabi_memcpy4", __aeabi_memcpy, linkage);
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@ -561,6 +563,14 @@ nakedcc fn ___chkstk_ms() align(4) void {
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);
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}
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extern fn __divmodsi4(a: i32, b: i32, rem: *i32) i32 {
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@setRuntimeSafety(is_test);
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const d = __divsi3(a, b);
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rem.* = a -% (d * b);
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return d;
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}
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extern fn __udivmodsi4(a: u32, b: u32, rem: *u32) u32 {
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@setRuntimeSafety(is_test);
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@ -1335,3 +1345,31 @@ fn test_one_divsi3(a: i32, b: i32, expected_q: i32) void {
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const q: i32 = __divsi3(a, b);
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testing.expect(q == expected_q);
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}
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test "test_divmodsi4" {
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const cases = [][4]i32{
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[]i32{ 0, 1, 0, 0},
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[]i32{ 0, -1, 0, 0},
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[]i32{ 2, 1, 2, 0},
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[]i32{ 2, -1, -2, 0},
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[]i32{-2, 1, -2, 0},
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[]i32{-2, -1, 2, 0},
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[]i32{ 7, 5, 1, 2},
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[]i32{-7, 5, -1, -2},
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[]i32{19, 5, 3, 4},
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[]i32{19, -5, -3, 4},
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[]i32{@bitCast(i32, u32(0x80000000)), 8, @bitCast(i32, u32(0xf0000000)), 0},
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[]i32{@bitCast(i32, u32(0x80000007)), 8, @bitCast(i32, u32(0xf0000001)), -1},
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};
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for (cases) |case| {
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test_one_divmodsi4(case[0], case[1], case[2], case[3]);
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}
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}
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fn test_one_divmodsi4(a: i32, b: i32, expected_q: i32, expected_r: i32) void {
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var r: i32 = undefined;
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const q: i32 = __divmodsi4(a, b, &r);
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testing.expect(q == expected_q and r == expected_r);
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}
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