cleanup CPU model & feature detection
Add std.Target.Cpu.Model.generic which is even more empty than baseline. CPU model and feature detection uses this rather than baseline. Rename cpu_detected to cpu_detection_unimplemented and flip the logic. It can be relied on by stage2.zig to decide whether the LLVM workaround is needed without also checking the CrossTarget. Move the CPU detection to after the OS detection, and use the detected OS for the CPU detection. This is relevant because operating systems sometimes emulate certain CPU features, so knowing the OS and version is relevant for determining CPU features. Prepare for #4592 by passing the CPU arch to the detection code, instead of having it rely on Target.current. The CPU model & feature detection logic is modified. Before: * Detect actual features * Use as hint when detecting CPU model * Populate dependencies of CPU model features * Merge that into the actual features set After: * Detect actual features * Use as hint when detecting CPU model * Add known CPU model features to actual features * Detect actual features again, overriding known CPU model features * Populate dependenciesmaster
Andrew Kelley
parent
f199182567
commit
49817c6add
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@ -907,7 +907,7 @@ pub const Target = struct {
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};
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}
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pub fn baseline(arch: Arch) *const Model {
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pub fn generic(arch: Arch) *const Model {
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const S = struct {
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const generic_model = Model{
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.name = "generic",
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@ -916,7 +916,7 @@ pub const Target = struct {
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};
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};
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return switch (arch) {
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.arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
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.arm, .armeb, .thumb, .thumbeb => &arm.cpu.generic,
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.aarch64, .aarch64_be, .aarch64_32 => &aarch64.cpu.generic,
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.avr => &avr.cpu.avr1,
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.bpfel, .bpfeb => &bpf.cpu.generic,
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@ -926,11 +926,11 @@ pub const Target = struct {
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.msp430 => &msp430.cpu.generic,
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.powerpc, .powerpc64, .powerpc64le => &powerpc.cpu.generic,
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.amdgcn => &amdgpu.cpu.generic,
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.riscv32 => &riscv.cpu.baseline_rv32,
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.riscv64 => &riscv.cpu.baseline_rv64,
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.riscv32 => &riscv.cpu.generic_rv32,
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.riscv64 => &riscv.cpu.generic_rv64,
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.sparc, .sparcv9, .sparcel => &sparc.cpu.generic,
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.s390x => &systemz.cpu.generic,
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.i386 => &x86.cpu.pentium4,
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.i386 => &x86.cpu._i386,
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.x86_64 => &x86.cpu.x86_64,
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.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
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.wasm32, .wasm64 => &wasm.cpu.generic,
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@ -938,6 +938,18 @@ pub const Target = struct {
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else => &S.generic_model,
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};
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}
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pub fn baseline(arch: Arch) *const Model {
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return switch (arch) {
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.arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
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.riscv32 => &riscv.cpu.baseline_rv32,
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.riscv64 => &riscv.cpu.baseline_rv64,
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.i386 => &x86.cpu.pentium4,
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.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
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else => generic(arch),
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};
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}
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};
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/// The "default" set of CPU features for cross-compiling. A conservative set
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@ -171,7 +171,10 @@ pub const NativeTargetInfo = struct {
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dynamic_linker: DynamicLinker = DynamicLinker{},
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cpu_detected: bool = false,
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/// Only some architectures have CPU detection implemented. This field reveals whether
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/// CPU detection actually occurred. When this is `true` it means that the reported
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/// CPU is baseline only because of a missing implementation for that architecture.
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cpu_detection_unimplemented: bool = false,
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pub const DynamicLinker = Target.DynamicLinker;
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@ -193,28 +196,6 @@ pub const NativeTargetInfo = struct {
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/// deinitialization method.
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/// TODO Remove the Allocator requirement from this function.
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pub fn detect(allocator: *Allocator, cross_target: CrossTarget) DetectError!NativeTargetInfo {
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var cpu_detected = true;
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const cpu = switch (cross_target.cpu_model) {
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.native => detectNativeCpuAndFeatures(cross_target),
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.baseline => baselineCpuAndFeatures(cross_target),
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.determined_by_cpu_arch => if (cross_target.cpu_arch == null)
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detectNativeCpuAndFeatures(cross_target)
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else
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baselineCpuAndFeatures(cross_target),
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.explicit => |model| blk: {
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var adjusted_model = model.toCpu(cross_target.getCpuArch());
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cross_target.updateCpuFeatures(&adjusted_model.features);
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break :blk adjusted_model;
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},
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} orelse backup_cpu_detection: {
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// Temporarily use LLVM's cpu info as a backup
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cpu_detected = false;
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break :backup_cpu_detection baselineCpuAndFeatures(cross_target);
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};
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var os = Target.Os.defaultVersionRange(cross_target.getOsTag());
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if (cross_target.os_tag == null) {
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switch (Target.current.os.tag) {
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@ -299,9 +280,12 @@ pub const NativeTargetInfo = struct {
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}
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},
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.freebsd => {
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// TODO Detect native operating system version.
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// Unimplemented, fall back to default.
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// https://github.com/ziglang/zig/issues/4582
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},
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else => {
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// Unimplemented, fall back to default version range.
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},
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else => {},
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}
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}
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@ -328,8 +312,31 @@ pub const NativeTargetInfo = struct {
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os.version_range.linux.glibc = glibc;
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}
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var cpu_detection_unimplemented = false;
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// Until https://github.com/ziglang/zig/issues/4592 is implemented (support detecting the
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// native CPU architecture as being different than the current target), we use this:
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const cpu_arch = cross_target.getCpuArch();
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const cpu = switch (cross_target.cpu_model) {
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.native => detectNativeCpuAndFeatures(cpu_arch, os, cross_target),
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.baseline => baselineCpuAndFeatures(cpu_arch, cross_target),
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.determined_by_cpu_arch => if (cross_target.cpu_arch == null)
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detectNativeCpuAndFeatures(cpu_arch, os, cross_target)
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else
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baselineCpuAndFeatures(cpu_arch, cross_target),
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.explicit => |model| blk: {
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var adjusted_model = model.toCpu(cpu_arch);
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cross_target.updateCpuFeatures(&adjusted_model.features);
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break :blk adjusted_model;
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},
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} orelse backup_cpu_detection: {
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cpu_detection_unimplemented = true;
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break :backup_cpu_detection baselineCpuAndFeatures(cpu_arch, cross_target);
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};
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var target = try detectAbiAndDynamicLinker(allocator, cpu, os, cross_target);
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target.cpu_detected = cpu_detected;
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target.cpu_detection_unimplemented = cpu_detection_unimplemented;
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return target;
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}
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@ -855,22 +862,22 @@ pub const NativeTargetInfo = struct {
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}
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}
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fn detectNativeCpuAndFeatures(cross_target: CrossTarget) ?Target.Cpu {
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switch(Target.current.cpu.arch) {
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fn detectNativeCpuAndFeatures(cpu_arch: Target.Cpu.Arch, os: Target.Os, cross_target: CrossTarget) ?Target.Cpu {
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switch (cpu_arch) {
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.x86_64, .i386 => {
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return @import("system/x86.zig").detectNativeCpuAndFeatures(cross_target);
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return @import("system/x86.zig").detectNativeCpuAndFeatures(cpu_arch, os, cross_target);
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},
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else => {
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// TODO flesh out CPU detection for more than just x86.
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// This architecture does not have CPU model & feature detection yet.
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// See https://github.com/ziglang/zig/issues/4591
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return null;
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}
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},
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}
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}
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fn baselineCpuAndFeatures(cross_target: CrossTarget) Target.Cpu {
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var adjusted_baseline = Target.Cpu.baseline(cross_target.getCpuArch());
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fn baselineCpuAndFeatures(cpu_arch: Target.Cpu.Arch, cross_target: CrossTarget) Target.Cpu {
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var adjusted_baseline = Target.Cpu.baseline(cpu_arch);
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cross_target.updateCpuFeatures(&adjusted_baseline.features);
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return adjusted_baseline;
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}
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};
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};
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@ -3,35 +3,30 @@ const Target = std.Target;
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const CrossTarget = std.zig.CrossTarget;
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fn setFeature(cpu: *Target.Cpu, feature: Target.x86.Feature, enabled: bool) void {
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const idx = @as(Target.Cpu.Feature.Set.Index, @enumToInt(feature));
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if(enabled) cpu.features.addFeature(idx)
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else cpu.features.removeFeature(idx);
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if (enabled) cpu.features.addFeature(idx) else cpu.features.removeFeature(idx);
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}
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inline fn bit(input: u32, offset: u5) bool {
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return (input >> offset) & 1 != 0;
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}
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pub fn detectNativeCpuAndFeatures(cross_target: CrossTarget) Target.Cpu {
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var arch = cross_target.getCpuArch();
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var cpu = Target.Cpu {
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pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, os: Target.Os, cross_target: CrossTarget) Target.Cpu {
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var cpu = Target.Cpu{
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.arch = arch,
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.model = Target.Cpu.Model.baseline(arch),
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.model = Target.Cpu.Model.generic(arch),
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.features = Target.Cpu.Feature.Set.empty,
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};
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detectNativeFeatures(&cpu, cross_target.getOsTag());
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// First we detect features, to use as hints when detecting CPU Model.
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detectNativeFeatures(&cpu, os.tag);
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var leaf = cpuid(0, 0);
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const max_leaf = leaf.eax;
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const vendor = leaf.ebx;
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if(max_leaf > 0) {
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if (max_leaf > 0) {
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leaf = cpuid(0x1, 0);
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const brand_id = leaf.ebx & 0xff;
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}
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}
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switch(vendor) {
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// Now we detect the model.
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switch (vendor) {
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0x756e6547 => {
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detectIntelProcessor(&cpu, family, model, brand_id);
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},
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@ -60,19 +56,21 @@ pub fn detectNativeCpuAndFeatures(cross_target: CrossTarget) Target.Cpu {
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}
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}
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var model_features = cpu.model.features;
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model_features.populateDependencies(cpu.arch.allFeaturesList());
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cpu.features.addFeatureSet(model_features);
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// Add the CPU model's feature set into the working set, but then
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// override with actual detected features again.
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cpu.features.addFeatureSet(cpu.model.features);
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detectNativeFeatures(&cpu, os.tag);
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cpu.features.populateDependencies(cpu.arch.allFeaturesList());
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return cpu;
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}
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fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32) void {
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if (brand_id != 0) {
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return;
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}
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switch(family) {
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switch (family) {
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3 => {
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cpu.model = &Target.x86.cpu._i386;
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return;
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@ -82,7 +80,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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5 => {
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if(Target.x86.featureSetHas(cpu.features, .mmx)) {
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if (Target.x86.featureSetHas(cpu.features, .mmx)) {
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cpu.model = &Target.x86.cpu.pentium_mmx;
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return;
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}
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@ -90,7 +88,7 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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6 => {
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switch(model) {
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switch (model) {
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0x01 => {
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cpu.model = &Target.x86.cpu.pentiumpro;
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return;
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@ -148,10 +146,10 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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return;
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},
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0x55 => {
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if(Target.x86.featureSetHas(cpu.features, .avx512bf16)) {
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if (Target.x86.featureSetHas(cpu.features, .avx512bf16)) {
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cpu.model = &Target.x86.cpu.cooperlake;
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return;
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} else if(Target.x86.featureSetHas(cpu.features, .avx512vnni)) {
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} else if (Target.x86.featureSetHas(cpu.features, .avx512vnni)) {
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cpu.model = &Target.x86.cpu.cascadelake;
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return;
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} else {
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@ -199,45 +197,36 @@ fn detectIntelProcessor(cpu: *Target.Cpu, family: u32, model: u32, brand_id: u32
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cpu.model = &Target.x86.cpu.knm;
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return;
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},
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else => {
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// Unknown CPU.
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// Default to baseline x86_64 or i386 cpu.
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return;
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},
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else => return, // Unknown CPU Model
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}
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},
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15 => {
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if(Target.x86.featureSetHas(cpu.features, .@"64bit")) {
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if (Target.x86.featureSetHas(cpu.features, .@"64bit")) {
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cpu.model = &Target.x86.cpu.nocona;
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return;
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}
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if(Target.x86.featureSetHas(cpu.features, .sse3)) {
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if (Target.x86.featureSetHas(cpu.features, .sse3)) {
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cpu.model = &Target.x86.cpu.prescott;
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return;
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}
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cpu.model = &Target.x86.cpu.pentium4;
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return;
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},
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else => {
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// Unknown CPU.
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// Default to baseline x86_64 or i386 cpu.
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return;
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}
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else => return, // Unknown CPU Model
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}
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}
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fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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// AMD's cpuid information is less than optimal for determining a CPU model.
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// This is very unscientific, and not necessarily correct.
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switch(family) {
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switch (family) {
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4 => {
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cpu.model = &Target.x86.cpu._i486;
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return;
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},
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5 => {
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cpu.model = &Target.x86.cpu.pentium;
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switch(model) {
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switch (model) {
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6, 7 => {
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cpu.model = &Target.x86.cpu.k6;
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return;
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@ -259,7 +248,7 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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return;
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},
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6 => {
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if(Target.x86.featureSetHas(cpu.features, .sse)) {
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if (Target.x86.featureSetHas(cpu.features, .sse)) {
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cpu.model = &Target.x86.cpu.athlon_xp;
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return;
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}
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@ -267,7 +256,7 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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return;
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},
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15 => {
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if(Target.x86.featureSetHas(cpu.features, .sse3)) {
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if (Target.x86.featureSetHas(cpu.features, .sse3)) {
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cpu.model = &Target.x86.cpu.k8_sse3;
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return;
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}
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@ -284,15 +273,15 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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},
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21 => {
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cpu.model = &Target.x86.cpu.bdver1;
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if(model >= 0x60 and model <= 0x7f) {
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if (model >= 0x60 and model <= 0x7f) {
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cpu.model = &Target.x86.cpu.bdver4;
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return;
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}
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if(model >= 0x30 and model <= 0x3f) {
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if (model >= 0x30 and model <= 0x3f) {
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cpu.model = &Target.x86.cpu.bdver3;
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return;
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}
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if((model >= 0x10 and model <= 0x1f) or model == 0x02) {
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if ((model >= 0x10 and model <= 0x1f) or model == 0x02) {
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cpu.model = &Target.x86.cpu.bdver2;
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return;
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}
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@ -304,7 +293,7 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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},
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23 => {
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cpu.model = &Target.x86.cpu.znver1;
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if((model >= 0x30 and model <= 0x3f) or model == 0x71) {
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if ((model >= 0x30 and model <= 0x3f) or model == 0x71) {
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cpu.model = &Target.x86.cpu.znver2;
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return;
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}
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@ -312,41 +301,40 @@ fn detectAMDProcessor(cpu: *Target.Cpu, family: u32, model: u32) void {
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},
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else => {
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return;
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}
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},
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}
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}
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fn detectNativeFeatures(cpu: *Target.Cpu, os_type: Target.Os.Tag) void {
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fn detectNativeFeatures(cpu: *Target.Cpu, os_tag: Target.Os.Tag) void {
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var leaf = cpuid(0, 0);
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const max_level = leaf.eax;
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leaf = cpuid(1, 0);
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setFeature(cpu, .cx8, bit(leaf.edx, 8));
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setFeature(cpu, .cx8, bit(leaf.edx, 8));
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setFeature(cpu, .cmov, bit(leaf.edx, 15));
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setFeature(cpu, .mmx, bit(leaf.edx, 23));
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setFeature(cpu, .fxsr, bit(leaf.edx, 24));
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setFeature(cpu, .sse, bit(leaf.edx, 25));
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setFeature(cpu, .sse2, bit(leaf.edx, 26));
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setFeature(cpu, .sse3, bit(leaf.ecx, 0));
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setFeature(cpu, .pclmul, bit(leaf.ecx, 1));
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setFeature(cpu, .ssse3, bit(leaf.ecx, 9));
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setFeature(cpu, .cx16, bit(leaf.ecx, 13));
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setFeature(cpu, .cx8, bit(leaf.edx, 8));
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setFeature(cpu, .cx8, bit(leaf.edx, 8));
|
||||
setFeature(cpu, .cmov, bit(leaf.edx, 15));
|
||||
setFeature(cpu, .mmx, bit(leaf.edx, 23));
|
||||
setFeature(cpu, .fxsr, bit(leaf.edx, 24));
|
||||
setFeature(cpu, .sse, bit(leaf.edx, 25));
|
||||
setFeature(cpu, .sse2, bit(leaf.edx, 26));
|
||||
setFeature(cpu, .sse3, bit(leaf.ecx, 0));
|
||||
setFeature(cpu, .pclmul, bit(leaf.ecx, 1));
|
||||
setFeature(cpu, .ssse3, bit(leaf.ecx, 9));
|
||||
setFeature(cpu, .cx16, bit(leaf.ecx, 13));
|
||||
setFeature(cpu, .sse4_1, bit(leaf.ecx, 19));
|
||||
setFeature(cpu, .sse4_2, bit(leaf.ecx, 20));
|
||||
setFeature(cpu, .movbe, bit(leaf.ecx, 22));
|
||||
setFeature(cpu, .movbe, bit(leaf.ecx, 22));
|
||||
setFeature(cpu, .popcnt, bit(leaf.ecx, 23));
|
||||
setFeature(cpu, .aes, bit(leaf.ecx, 25));
|
||||
setFeature(cpu, .rdrnd, bit(leaf.ecx, 30));
|
||||
setFeature(cpu, .aes, bit(leaf.ecx, 25));
|
||||
setFeature(cpu, .rdrnd, bit(leaf.ecx, 30));
|
||||
|
||||
leaf.eax = getXCR0();
|
||||
|
||||
const has_avx = bit(leaf.ecx, 27) and
|
||||
bit(leaf.ecx, 28) and
|
||||
((leaf.eax & 0x6) == 0x6);
|
||||
bit(leaf.ecx, 28) and
|
||||
((leaf.eax & 0x6) == 0x6);
|
||||
|
||||
// LLVM approaches avx512_save by hardcoding it to true on Darwin,
|
||||
// because the kernel saves the context even if the bit is not set.
|
||||
|
|
@ -368,96 +356,96 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_type: Target.Os.Tag) void {
|
|||
// Darwin lazily saves the AVX512 context on first use: trust that the OS will
|
||||
// save the AVX512 context if we use AVX512 instructions, even if the bit is not
|
||||
// set right now.
|
||||
const has_avx512_save = switch(os_type.isDarwin()) {
|
||||
true => true,
|
||||
const has_avx512_save = switch (os_tag.isDarwin()) {
|
||||
true => true,
|
||||
false => has_avx and ((leaf.eax & 0xE0) == 0xE0),
|
||||
};
|
||||
|
||||
setFeature(cpu, .avx, has_avx);
|
||||
setFeature(cpu, .fma, has_avx and bit(leaf.ecx, 12));
|
||||
setFeature(cpu, .avx, has_avx);
|
||||
setFeature(cpu, .fma, has_avx and bit(leaf.ecx, 12));
|
||||
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
||||
setFeature(cpu, .xsave, has_avx and bit(leaf.ecx, 26));
|
||||
setFeature(cpu, .f16c, has_avx and bit(leaf.ecx, 29));
|
||||
setFeature(cpu, .xsave, has_avx and bit(leaf.ecx, 26));
|
||||
setFeature(cpu, .f16c, has_avx and bit(leaf.ecx, 29));
|
||||
|
||||
leaf = cpuid(0x80000000, 0);
|
||||
const max_ext_level = leaf.eax;
|
||||
|
||||
if(max_ext_level >= 0x80000001) {
|
||||
if (max_ext_level >= 0x80000001) {
|
||||
leaf = cpuid(0x80000001, 0);
|
||||
setFeature(cpu, .sahf, bit(leaf.ecx, 0));
|
||||
setFeature(cpu, .lzcnt, bit(leaf.ecx, 5));
|
||||
setFeature(cpu, .sse4a, bit(leaf.ecx, 6));
|
||||
setFeature(cpu, .prfchw, bit(leaf.ecx, 8));
|
||||
setFeature(cpu, .xop, bit(leaf.ecx, 11) and has_avx);
|
||||
setFeature(cpu, .lwp, bit(leaf.ecx, 15));
|
||||
setFeature(cpu, .fma4, bit(leaf.ecx, 16) and has_avx);
|
||||
setFeature(cpu, .tbm, bit(leaf.ecx, 21));
|
||||
setFeature(cpu, .mwaitx, bit(leaf.ecx, 29));
|
||||
setFeature(cpu, .@"64bit", bit(leaf.edx, 29));
|
||||
setFeature(cpu, .sahf, bit(leaf.ecx, 0));
|
||||
setFeature(cpu, .lzcnt, bit(leaf.ecx, 5));
|
||||
setFeature(cpu, .sse4a, bit(leaf.ecx, 6));
|
||||
setFeature(cpu, .prfchw, bit(leaf.ecx, 8));
|
||||
setFeature(cpu, .xop, bit(leaf.ecx, 11) and has_avx);
|
||||
setFeature(cpu, .lwp, bit(leaf.ecx, 15));
|
||||
setFeature(cpu, .fma4, bit(leaf.ecx, 16) and has_avx);
|
||||
setFeature(cpu, .tbm, bit(leaf.ecx, 21));
|
||||
setFeature(cpu, .mwaitx, bit(leaf.ecx, 29));
|
||||
setFeature(cpu, .@"64bit", bit(leaf.edx, 29));
|
||||
} else {
|
||||
for([_]Target.x86.Feature{
|
||||
for ([_]Target.x86.Feature{
|
||||
.sahf, .lzcnt, .sse4a, .prfchw, .xop,
|
||||
.lwp, .fma4, .tbm, .mwaitx, .@"64bit"
|
||||
.lwp, .fma4, .tbm, .mwaitx, .@"64bit",
|
||||
}) |feat| {
|
||||
setFeature(cpu, feat, false);
|
||||
}
|
||||
}
|
||||
|
||||
// Misc. memory-related features.
|
||||
if(max_ext_level >= 0x80000008) {
|
||||
if (max_ext_level >= 0x80000008) {
|
||||
leaf = cpuid(0x80000008, 0);
|
||||
setFeature(cpu, .clzero, bit(leaf.ebx, 0));
|
||||
setFeature(cpu, .clzero, bit(leaf.ebx, 0));
|
||||
setFeature(cpu, .wbnoinvd, bit(leaf.ebx, 9));
|
||||
} else {
|
||||
for([_]Target.x86.Feature{ .clzero, .wbnoinvd }) |feat| {
|
||||
for ([_]Target.x86.Feature{ .clzero, .wbnoinvd }) |feat| {
|
||||
setFeature(cpu, feat, false);
|
||||
}
|
||||
}
|
||||
|
||||
if(max_level >= 0x7) {
|
||||
if (max_level >= 0x7) {
|
||||
leaf = cpuid(0x7, 0);
|
||||
|
||||
setFeature(cpu, .fsgsbase, bit(leaf.ebx, 0));
|
||||
setFeature(cpu, .sgx, bit(leaf.ebx, 2));
|
||||
setFeature(cpu, .bmi, bit(leaf.ebx, 3));
|
||||
setFeature(cpu, .fsgsbase, bit(leaf.ebx, 0));
|
||||
setFeature(cpu, .sgx, bit(leaf.ebx, 2));
|
||||
setFeature(cpu, .bmi, bit(leaf.ebx, 3));
|
||||
// AVX2 is only supported if we have the OS save support from AVX.
|
||||
setFeature(cpu, .avx2, bit(leaf.ebx, 5) and has_avx);
|
||||
setFeature(cpu, .bmi2, bit(leaf.ebx, 8));
|
||||
setFeature(cpu, .invpcid, bit(leaf.ebx, 10));
|
||||
setFeature(cpu, .rtm, bit(leaf.ebx, 11));
|
||||
setFeature(cpu, .avx2, bit(leaf.ebx, 5) and has_avx);
|
||||
setFeature(cpu, .bmi2, bit(leaf.ebx, 8));
|
||||
setFeature(cpu, .invpcid, bit(leaf.ebx, 10));
|
||||
setFeature(cpu, .rtm, bit(leaf.ebx, 11));
|
||||
// AVX512 is only supported if the OS supports the context save for it.
|
||||
setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
|
||||
setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
|
||||
setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
|
||||
setFeature(cpu, .adx, bit(leaf.ebx, 19));
|
||||
setFeature(cpu, .avx512ifma, bit(leaf.ebx, 21) and has_avx512_save);
|
||||
setFeature(cpu, .clflushopt, bit(leaf.ebx, 23));
|
||||
setFeature(cpu, .clwb, bit(leaf.ebx, 24));
|
||||
setFeature(cpu, .avx512pf, bit(leaf.ebx, 26) and has_avx512_save);
|
||||
setFeature(cpu, .avx512er, bit(leaf.ebx, 27) and has_avx512_save);
|
||||
setFeature(cpu, .avx512cd, bit(leaf.ebx, 28) and has_avx512_save);
|
||||
setFeature(cpu, .sha, bit(leaf.ebx, 29));
|
||||
setFeature(cpu, .avx512bw, bit(leaf.ebx, 30) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vl, bit(leaf.ebx, 31) and has_avx512_save);
|
||||
setFeature(cpu, .avx512f, bit(leaf.ebx, 16) and has_avx512_save);
|
||||
setFeature(cpu, .avx512dq, bit(leaf.ebx, 17) and has_avx512_save);
|
||||
setFeature(cpu, .rdseed, bit(leaf.ebx, 18));
|
||||
setFeature(cpu, .adx, bit(leaf.ebx, 19));
|
||||
setFeature(cpu, .avx512ifma, bit(leaf.ebx, 21) and has_avx512_save);
|
||||
setFeature(cpu, .clflushopt, bit(leaf.ebx, 23));
|
||||
setFeature(cpu, .clwb, bit(leaf.ebx, 24));
|
||||
setFeature(cpu, .avx512pf, bit(leaf.ebx, 26) and has_avx512_save);
|
||||
setFeature(cpu, .avx512er, bit(leaf.ebx, 27) and has_avx512_save);
|
||||
setFeature(cpu, .avx512cd, bit(leaf.ebx, 28) and has_avx512_save);
|
||||
setFeature(cpu, .sha, bit(leaf.ebx, 29));
|
||||
setFeature(cpu, .avx512bw, bit(leaf.ebx, 30) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vl, bit(leaf.ebx, 31) and has_avx512_save);
|
||||
|
||||
setFeature(cpu, .prefetchwt1, bit(leaf.ecx, 0));
|
||||
setFeature(cpu, .avx512vbmi, bit(leaf.ecx, 1) and has_avx512_save);
|
||||
setFeature(cpu, .pku, bit(leaf.ecx, 4));
|
||||
setFeature(cpu, .waitpkg, bit(leaf.ecx, 5));
|
||||
setFeature(cpu, .avx512vbmi2, bit(leaf.ecx, 6) and has_avx512_save);
|
||||
setFeature(cpu, .shstk, bit(leaf.ecx, 7));
|
||||
setFeature(cpu, .gfni, bit(leaf.ecx, 8));
|
||||
setFeature(cpu, .vaes, bit(leaf.ecx, 9) and has_avx);
|
||||
setFeature(cpu, .vpclmulqdq, bit(leaf.ecx, 10) and has_avx);
|
||||
setFeature(cpu, .avx512vnni, bit(leaf.ecx, 11) and has_avx512_save);
|
||||
setFeature(cpu, .avx512bitalg, bit(leaf.ecx, 12) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vpopcntdq, bit(leaf.ecx, 14) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vp2intersect, bit(leaf.edx, 8) and has_avx512_save);
|
||||
setFeature(cpu, .rdpid, bit(leaf.ecx, 22));
|
||||
setFeature(cpu, .cldemote, bit(leaf.ecx, 25));
|
||||
setFeature(cpu, .movdiri, bit(leaf.ecx, 27));
|
||||
setFeature(cpu, .movdir64b, bit(leaf.ecx, 28));
|
||||
setFeature(cpu, .enqcmd, bit(leaf.ecx, 29));
|
||||
setFeature(cpu, .prefetchwt1, bit(leaf.ecx, 0));
|
||||
setFeature(cpu, .avx512vbmi, bit(leaf.ecx, 1) and has_avx512_save);
|
||||
setFeature(cpu, .pku, bit(leaf.ecx, 4));
|
||||
setFeature(cpu, .waitpkg, bit(leaf.ecx, 5));
|
||||
setFeature(cpu, .avx512vbmi2, bit(leaf.ecx, 6) and has_avx512_save);
|
||||
setFeature(cpu, .shstk, bit(leaf.ecx, 7));
|
||||
setFeature(cpu, .gfni, bit(leaf.ecx, 8));
|
||||
setFeature(cpu, .vaes, bit(leaf.ecx, 9) and has_avx);
|
||||
setFeature(cpu, .vpclmulqdq, bit(leaf.ecx, 10) and has_avx);
|
||||
setFeature(cpu, .avx512vnni, bit(leaf.ecx, 11) and has_avx512_save);
|
||||
setFeature(cpu, .avx512bitalg, bit(leaf.ecx, 12) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vpopcntdq, bit(leaf.ecx, 14) and has_avx512_save);
|
||||
setFeature(cpu, .avx512vp2intersect, bit(leaf.edx, 8) and has_avx512_save);
|
||||
setFeature(cpu, .rdpid, bit(leaf.ecx, 22));
|
||||
setFeature(cpu, .cldemote, bit(leaf.ecx, 25));
|
||||
setFeature(cpu, .movdiri, bit(leaf.ecx, 27));
|
||||
setFeature(cpu, .movdir64b, bit(leaf.ecx, 28));
|
||||
setFeature(cpu, .enqcmd, bit(leaf.ecx, 29));
|
||||
|
||||
// There are two CPUID leafs which information associated with the pconfig
|
||||
// instruction:
|
||||
|
|
@ -469,21 +457,21 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_type: Target.Os.Tag) void {
|
|||
// leaves using cpuid, since that information is ignored while
|
||||
// detecting features using the "-march=native" flag.
|
||||
// For more info, see X86 ISA docs.
|
||||
setFeature(cpu, .pconfig, bit(leaf.edx, 18));
|
||||
setFeature(cpu, .pconfig, bit(leaf.edx, 18));
|
||||
|
||||
// TODO I feel unsure about this check.
|
||||
// It doesn't really seem to check for 7.1, just for 7.
|
||||
// Is this a sound assumption to make?
|
||||
// Note that this is what other implementations do, so I kind of trust it.
|
||||
const has_leaf_7_1 = max_level >= 7;
|
||||
if(has_leaf_7_1) {
|
||||
if (has_leaf_7_1) {
|
||||
leaf = cpuid(0x7, 0x1);
|
||||
setFeature(cpu, .avx512bf16, bit(leaf.eax, 5) and has_avx512_save);
|
||||
} else {
|
||||
setFeature(cpu, .avx512bf16, false);
|
||||
}
|
||||
} else {
|
||||
for([_]Target.x86.Feature{
|
||||
for ([_]Target.x86.Feature{
|
||||
.fsgsbase, .sgx, .bmi, .avx2,
|
||||
.bmi2, .invpcid, .rtm, .avx512f,
|
||||
.avx512dq, .rdseed, .adx, .avx512ifma,
|
||||
|
|
@ -499,26 +487,24 @@ fn detectNativeFeatures(cpu: *Target.Cpu, os_type: Target.Os.Tag) void {
|
|||
}
|
||||
}
|
||||
|
||||
if(max_level >= 0xD and has_avx) {
|
||||
if (max_level >= 0xD and has_avx) {
|
||||
leaf = cpuid(0xD, 0x1);
|
||||
// Only enable XSAVE if OS has enabled support for saving YMM state.
|
||||
setFeature(cpu, .xsaveopt, bit(leaf.eax, 0));
|
||||
setFeature(cpu, .xsavec, bit(leaf.eax, 1));
|
||||
setFeature(cpu, .xsaves, bit(leaf.eax, 3));
|
||||
|
||||
setFeature(cpu, .xsavec, bit(leaf.eax, 1));
|
||||
setFeature(cpu, .xsaves, bit(leaf.eax, 3));
|
||||
} else {
|
||||
for([_]Target.x86.Feature{ .xsaveopt, .xsavec, .xsaves }) |feat| {
|
||||
for ([_]Target.x86.Feature{ .xsaveopt, .xsavec, .xsaves }) |feat| {
|
||||
setFeature(cpu, feat, false);
|
||||
}
|
||||
}
|
||||
|
||||
if(max_level >= 0x14) {
|
||||
if (max_level >= 0x14) {
|
||||
leaf = cpuid(0x14, 0);
|
||||
setFeature(cpu, .ptwrite, bit(leaf.ebx, 4));
|
||||
} else {
|
||||
setFeature(cpu, .ptwrite, false);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
const CpuidLeaf = packed struct {
|
||||
|
|
@ -532,9 +518,9 @@ fn cpuid(leaf_id: u32, subid: u32) CpuidLeaf {
|
|||
// Workaround for https://github.com/ziglang/zig/issues/215
|
||||
// Inline assembly in zig only supports one output,
|
||||
// so we pass a pointer to the struct.
|
||||
var cpuid_leaf = CpuidLeaf {.eax = 0, .ebx = 0, .ecx = 0, .edx = 0};
|
||||
var cpuid_leaf = CpuidLeaf{ .eax = 0, .ebx = 0, .ecx = 0, .edx = 0 };
|
||||
var leaf_ptr = &cpuid_leaf;
|
||||
switch(Target.current.cpu.arch) {
|
||||
switch (Target.current.cpu.arch) {
|
||||
.i386 => {
|
||||
_ = asm volatile (
|
||||
\\ cpuid
|
||||
|
|
@ -542,10 +528,10 @@ fn cpuid(leaf_id: u32, subid: u32) CpuidLeaf {
|
|||
\\ movl %%ebx, 4(%%edi)
|
||||
\\ movl %%ecx, 8(%%edi)
|
||||
\\ movl %%edx, 12(%%edi)
|
||||
: :
|
||||
[leaf_id] "{eax}" (leaf_id),
|
||||
[subid] "{ecx}" (subid),
|
||||
[leaf_ptr] "{edi}" (leaf_ptr),
|
||||
:
|
||||
: [leaf_id] "{eax}" (leaf_id),
|
||||
[subid] "{ecx}" (subid),
|
||||
[leaf_ptr] "{edi}" (leaf_ptr)
|
||||
: "eax", "ebx", "ecx", "edx"
|
||||
);
|
||||
},
|
||||
|
|
@ -556,10 +542,10 @@ fn cpuid(leaf_id: u32, subid: u32) CpuidLeaf {
|
|||
\\ movl %%ebx, 4(%%rdi)
|
||||
\\ movl %%ecx, 8(%%rdi)
|
||||
\\ movl %%edx, 12(%%rdi)
|
||||
: :
|
||||
[leaf_id] "{eax}" (leaf_id),
|
||||
[subid] "{ecx}" (subid),
|
||||
[leaf_ptr] "{rdi}" (leaf_ptr),
|
||||
:
|
||||
: [leaf_id] "{eax}" (leaf_id),
|
||||
[subid] "{ecx}" (subid),
|
||||
[leaf_ptr] "{rdi}" (leaf_ptr)
|
||||
: "eax", "ebx", "ecx", "edx"
|
||||
);
|
||||
},
|
||||
|
|
@ -570,14 +556,11 @@ fn cpuid(leaf_id: u32, subid: u32) CpuidLeaf {
|
|||
|
||||
// Read control register 0 (XCR0). Used to detect features such as AVX.
|
||||
fn getXCR0() u32 {
|
||||
|
||||
return asm (
|
||||
\\ .byte 0x0F, 0x01, 0xD0
|
||||
: [ret] "={eax}" (-> u32)
|
||||
: [number] "{eax}" (@as(u32, 0)),
|
||||
[number] "{edx}" (@as(u32, 0)),
|
||||
[number] "{ecx}" (@as(u32, 0)),
|
||||
:
|
||||
[number] "{ecx}" (@as(u32, 0))
|
||||
);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1154,7 +1154,7 @@ fn enumInt(comptime Enum: type, int: c_int) Enum {
|
|||
|
||||
fn crossTargetToTarget(cross_target: CrossTarget, dynamic_linker_ptr: *?[*:0]u8) !Target {
|
||||
var info = try std.zig.system.NativeTargetInfo.detect(std.heap.c_allocator, cross_target);
|
||||
if ((cross_target.cpu_arch == null or cross_target.cpu_model == .native) and !info.cpu_detected) {
|
||||
if (info.cpu_detection_unimplemented) {
|
||||
// TODO We want to just use detected_info.target but implementing
|
||||
// CPU model & feature detection is todo so here we rely on LLVM.
|
||||
const llvm = @import("llvm.zig");
|
||||
|
|
|
|||
Loading…
Reference in New Issue