implemented and testing op codes for instructions documented in the unofficial bpf insn reference
Matt Knight
parent
32a77a6047
commit
295f09eadc
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@ -5,6 +5,7 @@
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// and substantial portions of the software.
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usingnamespace std.os;
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const std = @import("../../std.zig");
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const builtin = @import("builtin");
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const expectEqual = std.testing.expectEqual;
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// instruction classes
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@ -328,6 +329,8 @@ pub const Helper = enum(i32) {
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_,
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};
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// TODO: determine that this is the expected bit layout for both little and big
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// endian systems
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/// a single BPF instruction
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pub const Insn = packed struct {
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code: u8,
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@ -340,19 +343,30 @@ pub const Insn = packed struct {
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/// frame
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pub const Reg = packed enum(u4) { r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 };
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const Source = packed enum(u1) { reg, imm };
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const Mode = packed enum(u8) {
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imm = IMM,
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abs = ABS,
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ind = IND,
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mem = MEM,
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len = LEN,
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msh = MSH,
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};
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const AluOp = packed enum(u8) {
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add = ADD,
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sub = SUB,
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mul = MUL,
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div = DIV,
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op_or = OR,
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op_and = AND,
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alu_or = OR,
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alu_and = AND,
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lsh = LSH,
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rsh = RSH,
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neg = NEG,
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mod = MOD,
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xor = XOR,
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mov = MOV,
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arsh = ARSH,
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};
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pub const Size = packed enum(u8) {
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@ -368,6 +382,13 @@ pub const Insn = packed struct {
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jgt = JGT,
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jge = JGE,
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jset = JSET,
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jlt = JLT,
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jle = JLE,
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jne = JNE,
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jsgt = JSGT,
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jsge = JSGE,
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jslt = JSLT,
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jsle = JSLE,
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};
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const ImmOrReg = union(Source) {
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@ -419,14 +440,102 @@ pub const Insn = packed struct {
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return alu(64, .add, dst, src);
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}
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pub fn sub(dst: Reg, src: anytype) Insn {
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return alu(64, .sub, dst, src);
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}
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pub fn mul(dst: Reg, src: anytype) Insn {
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return alu(64, .mul, dst, src);
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}
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pub fn div(dst: Reg, src: anytype) Insn {
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return alu(64, .div, dst, src);
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}
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pub fn alu_or(dst: Reg, src: anytype) Insn {
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return alu(64, .alu_or, dst, src);
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}
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pub fn alu_and(dst: Reg, src: anytype) Insn {
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return alu(64, .alu_and, dst, src);
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}
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pub fn lsh(dst: Reg, src: anytype) Insn {
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return alu(64, .lsh, dst, src);
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}
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pub fn rsh(dst: Reg, src: anytype) Insn {
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return alu(64, .rsh, dst, src);
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}
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pub fn neg(dst: Reg) Insn {
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return alu(64, .neg, dst, 0);
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}
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pub fn mod(dst: Reg, src: anytype) Insn {
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return alu(64, .mod, dst, src);
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}
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pub fn xor(dst: Reg, src: anytype) Insn {
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return alu(64, .xor, dst, src);
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}
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pub fn arsh(dst: Reg, src: anytype) Insn {
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return alu(64, .arsh, dst, src);
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}
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fn jmp(op: JmpOp, dst: Reg, src: anytype, off: i16) Insn {
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return imm_reg(JMP | @enumToInt(op), dst, src, off);
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}
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pub fn ja(off: i16) Insn {
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return jmp(.ja, .r0, 0, off);
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}
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pub fn jeq(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jeq, dst, src, off);
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}
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pub fn jgt(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jgt, dst, src, off);
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}
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pub fn jge(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jge, dst, src, off);
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}
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pub fn jlt(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jlt, dst, src, off);
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}
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pub fn jle(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jle, dst, src, off);
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}
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pub fn jset(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jset, dst, src, off);
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}
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pub fn jne(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jne, dst, src, off);
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}
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pub fn jsgt(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jsgt, dst, src, off);
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}
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pub fn jsge(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jsge, dst, src, off);
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}
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pub fn jslt(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jslt, dst, src, off);
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}
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pub fn jsle(dst: Reg, src: anytype, off: i16) Insn {
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return jmp(.jsle, dst, src, off);
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}
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pub fn stx_mem(size: Size, dst: Reg, src: Reg, off: i16) Insn {
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return Insn{
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.code = STX | @enumToInt(size) | MEM,
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@ -447,17 +556,34 @@ pub const Insn = packed struct {
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};
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}
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/// direct packet access, R0 = *(uint *)(skb->data + imm32)
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pub fn ld_abs(size: Size, imm: i32) Insn {
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fn ld(mode: Mode, size: Size, dst: Reg, src: Reg, imm: i32) Insn {
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return Insn{
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.code = LD | @enumToInt(size) | ABS,
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.dst = 0,
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.src = 0,
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.code = @enumToInt(mode) | @enumToInt(size) | LD,
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.dst = @enumToInt(dst),
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.src = @enumToInt(src),
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.off = 0,
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.imm = imm,
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};
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}
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pub fn ld_abs(size: Size, dst: Reg, src: Reg, imm: i32) Insn {
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return ld(.abs, size, dst, src, imm);
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}
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pub fn ld_ind(size: Size, dst: Reg, src: Reg, imm: i32) Insn {
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return ld(.ind, size, dst, src, imm);
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}
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pub fn ldx(size: Size, dst: Reg, src: Reg, off: i16) Insn {
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return Insn{
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.code = MEM | @enumToInt(size) | LDX,
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.dst = @enumToInt(dst),
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.src = @enumToInt(src),
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.off = off,
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.imm = 0,
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};
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}
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fn ld_imm_impl1(dst: Reg, src: Reg, imm: u64) Insn {
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return Insn{
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.code = LD | DW | IMM,
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@ -478,6 +604,14 @@ pub const Insn = packed struct {
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};
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}
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pub fn ld_dw1(dst: Reg, imm: u64) Insn {
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return ld_imm_impl1(dst, .r0, imm);
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}
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pub fn ld_dw2(imm: u64) Insn {
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return ld_imm_impl2(imm);
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}
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pub fn ld_map_fd1(dst: Reg, map_fd: fd_t) Insn {
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return ld_imm_impl1(dst, @intToEnum(Reg, PSEUDO_MAP_FD), @intCast(u64, map_fd));
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}
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@ -486,6 +620,53 @@ pub const Insn = packed struct {
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return ld_imm_impl2(@intCast(u64, map_fd));
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}
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pub fn st(comptime size: Size, dst: Reg, off: i16, imm: i32) Insn {
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if (size == .double_word) @compileError("TODO: implement st_dw");
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return Insn{
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.code = MEM | @enumToInt(size) | ST,
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.dst = @enumToInt(dst),
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.src = 0,
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.off = off,
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.imm = imm,
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};
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}
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pub fn stx(size: Size, dst: Reg, off: i16, src: Reg) Insn {
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return Insn{
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.code = MEM | @enumToInt(size) | STX,
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.dst = @enumToInt(dst),
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.src = @enumToInt(src),
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.off = off,
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.imm = 0,
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};
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}
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fn endian_swap(endian: builtin.Endian, comptime size: Size, dst: Reg) Insn {
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return Insn{
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.code = switch (endian) {
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.Big => 0xdc,
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.Little => 0xd4,
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},
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.dst = @enumToInt(dst),
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.src = 0,
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.off = 0,
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.imm = switch (size) {
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.byte => @compileError("can't swap a single byte"),
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.half_word => 16,
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.word => 32,
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.double_word => 64,
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},
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};
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}
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pub fn le(comptime size: Size, dst: Reg) Insn {
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return endian_swap(.Little, size, dst);
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}
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pub fn be(comptime size: Size, dst: Reg) Insn {
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return endian_swap(.Big, size, dst);
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}
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pub fn call(helper: Helper) Insn {
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return Insn{
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.code = JMP | CALL,
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@ -508,59 +689,122 @@ pub const Insn = packed struct {
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}
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};
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fn expect_insn(insn: Insn, val: u64) void {
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expectEqual(@bitCast(u64, insn), val);
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}
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test "insn bitsize" {
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expectEqual(@bitSizeOf(Insn), 64);
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}
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// mov instructions
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test "mov imm" {
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expect_insn(Insn.mov(.r1, 1), 0x00000001000001b7);
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fn expect_opcode(code: u8, insn: Insn) void {
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expectEqual(code, insn.code);
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}
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test "mov reg" {
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expect_insn(Insn.mov(.r6, .r1), 0x00000000000016bf);
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}
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// The opcodes were grabbed from https://github.com/iovisor/bpf-docs/blob/master/eBPF.md
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test "opcodes" {
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// instructions that have a name that end with 1 or 2 are consecutive for
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// loading 64-bit immediates (imm is only 32 bits wide)
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// alu instructions
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test "add imm" {
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expect_insn(Insn.add(.r2, -4), 0xfffffffc00000207);
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}
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// alu instructions
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expect_opcode(0x07, Insn.add(.r1, 0));
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expect_opcode(0x0f, Insn.add(.r1, .r2));
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expect_opcode(0x17, Insn.sub(.r1, 0));
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expect_opcode(0x1f, Insn.sub(.r1, .r2));
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expect_opcode(0x27, Insn.mul(.r1, 0));
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expect_opcode(0x2f, Insn.mul(.r1, .r2));
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expect_opcode(0x37, Insn.div(.r1, 0));
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expect_opcode(0x3f, Insn.div(.r1, .r2));
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expect_opcode(0x47, Insn.alu_or(.r1, 0));
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expect_opcode(0x4f, Insn.alu_or(.r1, .r2));
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expect_opcode(0x57, Insn.alu_and(.r1, 0));
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expect_opcode(0x5f, Insn.alu_and(.r1, .r2));
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expect_opcode(0x67, Insn.lsh(.r1, 0));
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expect_opcode(0x6f, Insn.lsh(.r1, .r2));
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expect_opcode(0x77, Insn.rsh(.r1, 0));
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expect_opcode(0x7f, Insn.rsh(.r1, .r2));
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expect_opcode(0x87, Insn.neg(.r1));
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expect_opcode(0x97, Insn.mod(.r1, 0));
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expect_opcode(0x9f, Insn.mod(.r1, .r2));
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expect_opcode(0xa7, Insn.xor(.r1, 0));
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expect_opcode(0xaf, Insn.xor(.r1, .r2));
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expect_opcode(0xb7, Insn.mov(.r1, 0));
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expect_opcode(0xbf, Insn.mov(.r1, .r2));
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expect_opcode(0xc7, Insn.arsh(.r1, 0));
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expect_opcode(0xcf, Insn.arsh(.r1, .r2));
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// ld instructions
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test "ld_abs" {
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expect_insn(Insn.ld_abs(.byte, 42), 0x0000002a00000030);
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}
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// atomic instructions: might be more of these not documented in the wild
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expect_opcode(0xdb, Insn.xadd(.r1, .r2));
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test "ld_map_fd" {
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expect_insn(Insn.ld_map_fd1(.r1, 42), 0x0000002a00001118);
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expect_insn(Insn.ld_map_fd2(42), 0x0000000000000000);
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}
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// TODO: byteswap instructions
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expect_opcode(0xd4, Insn.le(.half_word, .r1));
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expectEqual(@intCast(i32, 16), Insn.le(.half_word, .r1).imm);
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expect_opcode(0xd4, Insn.le(.word, .r1));
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expectEqual(@intCast(i32, 32), Insn.le(.word, .r1).imm);
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expect_opcode(0xd4, Insn.le(.double_word, .r1));
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expectEqual(@intCast(i32, 64), Insn.le(.double_word, .r1).imm);
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expect_opcode(0xdc, Insn.be(.half_word, .r1));
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expectEqual(@intCast(i32, 16), Insn.be(.half_word, .r1).imm);
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expect_opcode(0xdc, Insn.be(.word, .r1));
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expectEqual(@intCast(i32, 32), Insn.be(.word, .r1).imm);
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expect_opcode(0xdc, Insn.be(.double_word, .r1));
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expectEqual(@intCast(i32, 64), Insn.be(.double_word, .r1).imm);
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// st instructions
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test "stx_mem" {
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expect_insn(Insn.stx_mem(.word, .r10, .r0, -4), 0x00000000fffc0a63);
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}
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// memory instructions
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expect_opcode(0x18, Insn.ld_dw1(.r1, 0));
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expect_opcode(0x00, Insn.ld_dw2(0));
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test "xadd" {
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expect_insn(Insn.xadd(.r0, .r1), 0x00000000000010db);
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}
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// loading a map fd
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expect_opcode(0x18, Insn.ld_map_fd1(.r1, 0));
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expectEqual(@intCast(u4, PSEUDO_MAP_FD), Insn.ld_map_fd1(.r1, 0).src);
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expect_opcode(0x00, Insn.ld_map_fd2(0));
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// jmp instructions
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test "jeq imm" {
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expect_insn(Insn.jeq(.r0, 0, 2), 0x0000000000020015);
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}
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expect_opcode(0x38, Insn.ld_abs(.double_word, .r1, .r2, 0));
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expect_opcode(0x20, Insn.ld_abs(.word, .r1, .r2, 0));
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expect_opcode(0x28, Insn.ld_abs(.half_word, .r1, .r2, 0));
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expect_opcode(0x30, Insn.ld_abs(.byte, .r1, .r2, 0));
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// other instructions
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test "call" {
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expect_insn(Insn.call(.map_lookup_elem), 0x0000000100000085);
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}
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expect_opcode(0x58, Insn.ld_ind(.double_word, .r1, .r2, 0));
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expect_opcode(0x40, Insn.ld_ind(.word, .r1, .r2, 0));
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expect_opcode(0x48, Insn.ld_ind(.half_word, .r1, .r2, 0));
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expect_opcode(0x50, Insn.ld_ind(.byte, .r1, .r2, 0));
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test "exit" {
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expect_insn(Insn.exit(), 0x0000000000000095);
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expect_opcode(0x79, Insn.ldx(.double_word, .r1, .r2, 0));
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expect_opcode(0x61, Insn.ldx(.word, .r1, .r2, 0));
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expect_opcode(0x69, Insn.ldx(.half_word, .r1, .r2, 0));
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expect_opcode(0x71, Insn.ldx(.byte, .r1, .r2, 0));
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expect_opcode(0x62, Insn.st(.word, .r1, 0, 0));
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expect_opcode(0x6a, Insn.st(.half_word, .r1, 0, 0));
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expect_opcode(0x72, Insn.st(.byte, .r1, 0, 0));
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expect_opcode(0x63, Insn.stx(.word, .r1, 0, .r2));
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expect_opcode(0x6b, Insn.stx(.half_word, .r1, 0, .r2));
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expect_opcode(0x73, Insn.stx(.byte, .r1, 0, .r2));
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expect_opcode(0x7b, Insn.stx(.double_word, .r1, 0, .r2));
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// branch instructions
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expect_opcode(0x05, Insn.ja(0));
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expect_opcode(0x15, Insn.jeq(.r1, 0, 0));
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expect_opcode(0x1d, Insn.jeq(.r1, .r2, 0));
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expect_opcode(0x25, Insn.jgt(.r1, 0, 0));
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expect_opcode(0x2d, Insn.jgt(.r1, .r2, 0));
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expect_opcode(0x35, Insn.jge(.r1, 0, 0));
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expect_opcode(0x3d, Insn.jge(.r1, .r2, 0));
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expect_opcode(0xa5, Insn.jlt(.r1, 0, 0));
|
||||
expect_opcode(0xad, Insn.jlt(.r1, .r2, 0));
|
||||
expect_opcode(0xb5, Insn.jle(.r1, 0, 0));
|
||||
expect_opcode(0xbd, Insn.jle(.r1, .r2, 0));
|
||||
expect_opcode(0x45, Insn.jset(.r1, 0, 0));
|
||||
expect_opcode(0x4d, Insn.jset(.r1, .r2, 0));
|
||||
expect_opcode(0x55, Insn.jne(.r1, 0, 0));
|
||||
expect_opcode(0x5d, Insn.jne(.r1, .r2, 0));
|
||||
expect_opcode(0x65, Insn.jsgt(.r1, 0, 0));
|
||||
expect_opcode(0x6d, Insn.jsgt(.r1, .r2, 0));
|
||||
expect_opcode(0x75, Insn.jsge(.r1, 0, 0));
|
||||
expect_opcode(0x7d, Insn.jsge(.r1, .r2, 0));
|
||||
expect_opcode(0xc5, Insn.jslt(.r1, 0, 0));
|
||||
expect_opcode(0xcd, Insn.jslt(.r1, .r2, 0));
|
||||
expect_opcode(0xd5, Insn.jsle(.r1, 0, 0));
|
||||
expect_opcode(0xdd, Insn.jsle(.r1, .r2, 0));
|
||||
expect_opcode(0x85, Insn.call(.unspec));
|
||||
expect_opcode(0x95, Insn.exit());
|
||||
}
|
||||
|
||||
pub const Cmd = extern enum(usize) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue