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Fix CPU and feature defs

master
Layne Gustafson 2019-12-17 09:45:00 -05:00 committed by Andrew Kelley
parent 8ac138a318
commit 21908e100e
No known key found for this signature in database
GPG Key ID: 7C5F548F728501A9
34 changed files with 5315 additions and 5307 deletions
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12
lib/std/target/cpu.zig
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@ -1,7 +1,7 @@
const std = @import("std");
const feature = @import("feature.zig");
const Arch = @import("arch.zig").Arch;
const Arch = std.Target.Arch;
pub const AArch64Cpu = @import("cpu/AArch64Cpu.zig").AArch64Cpu;
pub const AmdGpuCpu = @import("cpu/AmdGpuCpu.zig").AmdGpuCpu;
@ -19,7 +19,7 @@ pub const SystemZCpu = @import("cpu/SystemZCpu.zig").SystemZCpu;
pub const WebAssemblyCpu = @import("cpu/WebAssemblyCpu.zig").WebAssemblyCpu;
pub const X86Cpu = @import("cpu/X86Cpu.zig").X86Cpu;
const EmptyCpu = @import("feature/empty.zig").EmptyCpu;
pub const EmptyCpu = @import("cpu/empty.zig").EmptyCpu;
pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
return switch (arch) {
@ -44,19 +44,21 @@ pub fn ArchCpu(comptime arch: @TagType(Arch)) type {
}
pub fn ArchCpuInfo(comptime arch: @TagType(Arch)) type {
return CpuInfo(feature.ArchFeature(arch));
return CpuInfo(ArchCpu(arch), feature.ArchFeature(arch));
}
pub fn CpuInfo(comptime FeatureType: type) type {
pub fn CpuInfo(comptime CpuType: type, comptime FeatureType: type) type {
return struct {
value: CpuType,
name: []const u8,
features: []const FeatureType,
const Self = @This();
fn create(name: []const u8, features: []const FeatureType) Self {
pub fn create(value: CpuType, name: []const u8, features: []const FeatureType) Self {
return Self {
.value = value,
.name = name,
.features = features,
};

608
lib/std/target/cpu/AArch64Cpu.zig
View File

@ -33,298 +33,298 @@ pub const AArch64Cpu = enum {
Thunderxt88,
Tsv110,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.AArch64Feature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.AArch64Feature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.AppleLatest, "apple-latest", &[_]FeatureType {
.ZczFp,
.ArithCbzFusion,
.FuseAes,
.AlternateSextloadCvtF32Pattern,
.ZczFpWorkaround,
.FpArmv8,
.Perfmon,
.DisableLatencySchedHeuristic,
.Zcm,
.ZczGp,
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.AppleLatest, "apple-latest", &[_]FeatureType {
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
.Cyclone,
},
CpuInfo(@This()).create(.CortexA35, "cortex-a35", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA35, "cortex-a35", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.A35,
},
CpuInfo(@This()).create(.CortexA53, "cortex-a53", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA53, "cortex-a53", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.BalanceFpOps,
.UseAa,
.FuseAes,
.FpArmv8,
.Perfmon,
.Crc,
.BalanceFpOps,
.UsePostraScheduler,
.CustomCheapAsMove,
.FuseAes,
.A53,
},
CpuInfo(@This()).create(.CortexA55, "cortex-a55", &[_]FeatureType {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Perfmon,
.FpArmv8,
}),
CpuInfo(@This(), FeatureType).create(.CortexA55, "cortex-a55", &[_]FeatureType {
.Lse,
.Crc,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Vh,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
.A55,
},
CpuInfo(@This()).create(.CortexA57, "cortex-a57", &[_]FeatureType {
.FuseLiterals,
.FuseAes,
.FpArmv8,
}),
CpuInfo(@This(), FeatureType).create(.CortexA57, "cortex-a57", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.BalanceFpOps,
.UsePostraScheduler,
.CustomCheapAsMove,
.PredictableSelectExpensive,
.FuseLiterals,
.FpArmv8,
.FuseAes,
.A57,
},
CpuInfo(@This()).create(.CortexA65, "cortex-a65", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA65, "cortex-a65", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
.A65,
},
CpuInfo(@This()).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA65ae, "cortex-a65ae", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
.A65,
},
CpuInfo(@This()).create(.CortexA72, "cortex-a72", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA72, "cortex-a72", &[_]FeatureType {
.Perfmon,
.FuseAes,
.FpArmv8,
.Crc,
.FuseAes,
.A72,
},
CpuInfo(@This()).create(.CortexA73, "cortex-a73", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA73, "cortex-a73", &[_]FeatureType {
.Perfmon,
.FuseAes,
.FpArmv8,
.Crc,
.FuseAes,
.A73,
},
CpuInfo(@This()).create(.CortexA75, "cortex-a75", &[_]FeatureType {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Perfmon,
.FpArmv8,
}),
CpuInfo(@This(), FeatureType).create(.CortexA75, "cortex-a75", &[_]FeatureType {
.Lse,
.Crc,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Vh,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
.A75,
},
CpuInfo(@This()).create(.CortexA76, "cortex-a76", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA76, "cortex-a76", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
.A76,
},
CpuInfo(@This()).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CortexA76ae, "cortex-a76ae", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
.A76,
},
CpuInfo(@This()).create(.Cyclone, "cyclone", &[_]FeatureType {
.ZczFp,
}),
CpuInfo(@This(), FeatureType).create(.Cyclone, "cyclone", &[_]FeatureType {
.ArithBccFusion,
.ArithCbzFusion,
.FuseAes,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.ZczFpWorkaround,
.FpArmv8,
.Perfmon,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.ZczGp,
.ArithBccFusion,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
.Cyclone,
},
CpuInfo(@This()).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.ExynosM1, "exynos-m1", &[_]FeatureType {
.ZczFp,
.FuseAes,
.SlowPaired128,
.Force32bitJumpTables,
.Perfmon,
.UsePostraScheduler,
.Crc,
.UseReciprocalSquareRoot,
.FpArmv8,
.Perfmon,
.SlowMisaligned128store,
.Crc,
.UsePostraScheduler,
.CustomCheapAsMove,
.Exynosm1,
},
CpuInfo(@This()).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
.ZczFp,
.FuseAes,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.Force32bitJumpTables,
.FpArmv8,
.FuseAes,
.Exynosm1,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM2, "exynos-m2", &[_]FeatureType {
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.Crc,
.UsePostraScheduler,
.CustomCheapAsMove,
.FpArmv8,
.SlowPaired128,
.FuseAes,
.Exynosm2,
},
CpuInfo(@This()).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
.ZczFp,
.FuseLiterals,
.FuseAes,
.Force32bitJumpTables,
.FpArmv8,
.Perfmon,
.Crc,
.LslFast,
.FuseAddress,
.UsePostraScheduler,
.CustomCheapAsMove,
.PredictableSelectExpensive,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM3, "exynos-m3", &[_]FeatureType {
.FuseCsel,
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.Force32bitJumpTables,
.FuseLiterals,
.FuseAddress,
.LslFast,
.FpArmv8,
.FuseAes,
.Exynosm3,
},
CpuInfo(@This()).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
.ZczFp,
.Lse,
.FuseArithLogic,
.Lor,
.UsePostraScheduler,
.Uaops,
.CustomCheapAsMove,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM4, "exynos-m4", &[_]FeatureType {
.ArithBccFusion,
.Ccpp,
.Perfmon,
.Pan,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.FuseLiterals,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.Ras,
.FuseCsel,
.ArithCbzFusion,
.FuseAes,
.FpArmv8,
.Crc,
.Dotprod,
.Vh,
.FuseAes,
.Exynosm4,
},
CpuInfo(@This()).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
.ZczFp,
.Lse,
.FuseArithLogic,
.Lor,
.UsePostraScheduler,
.Uaops,
.CustomCheapAsMove,
}),
CpuInfo(@This(), FeatureType).create(.ExynosM5, "exynos-m5", &[_]FeatureType {
.ArithBccFusion,
.Ccpp,
.Perfmon,
.Pan,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.FuseLiterals,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.Ras,
.FuseCsel,
.ArithCbzFusion,
.FuseAes,
.FpArmv8,
.Crc,
.Dotprod,
.Vh,
.FuseAes,
.Exynosm4,
},
CpuInfo(@This()).create(.Falkor, "falkor", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Falkor, "falkor", &[_]FeatureType {
.ZczFp,
.Rdm,
.SlowStrqroStore,
.Perfmon,
.FpArmv8,
.Crc,
.LslFast,
.UsePostraScheduler,
.ZczGp,
.CustomCheapAsMove,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.SlowStrqroStore,
.LslFast,
.Falkor,
},
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.Trbe,
.Ete,
.FpArmv8,
@ -332,149 +332,149 @@ pub const AArch64Cpu = enum {
.Neon,
.Perfmon,
.UsePostraScheduler,
},
CpuInfo(@This()).create(.Kryo, "kryo", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Kryo, "kryo", &[_]FeatureType {
.ZczFp,
.Perfmon,
.FpArmv8,
.Crc,
.LslFast,
.UsePostraScheduler,
.ZczGp,
.CustomCheapAsMove,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.LslFast,
.Kryo,
},
CpuInfo(@This()).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.NeoverseE1, "neoverse-e1", &[_]FeatureType {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
.Neoversee1,
},
CpuInfo(@This()).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
.Rcpc,
.Spe,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
}),
CpuInfo(@This(), FeatureType).create(.NeoverseN1, "neoverse-n1", &[_]FeatureType {
.Lse,
.Crc,
.Spe,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Lor,
.Crc,
.Ssbs,
.Uaops,
.Vh,
.Ras,
.Neoversen1,
},
CpuInfo(@This()).create(.Saphira, "saphira", &[_]FeatureType {
.ZczFp,
.Nv,
.Am,
.Lse,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.UsePostraScheduler,
.CustomCheapAsMove,
.Ccpp,
.Perfmon,
.TlbRmi,
.PredictableSelectExpensive,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.LslFast,
.Pa,
.ZczGp,
.Dit,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.Neoversen1,
}),
CpuInfo(@This(), FeatureType).create(.Saphira, "saphira", &[_]FeatureType {
.Spe,
.Mpam,
.FpArmv8,
.Ccidx,
.Dotprod,
.Crc,
.Vh,
.Saphira,
},
CpuInfo(@This()).create(.Thunderx, "thunderx", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.LslFast,
.Lse,
.Nv,
.Perfmon,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.PredictableSelectExpensive,
.Crc,
.CustomCheapAsMove,
.Fmi,
.ZczGp,
.FpArmv8,
.Saphira,
}),
CpuInfo(@This(), FeatureType).create(.Thunderx, "thunderx", &[_]FeatureType {
.Perfmon,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderx,
},
CpuInfo(@This()).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
.Pan,
.Rdm,
}),
CpuInfo(@This(), FeatureType).create(.Thunderx2t99, "thunderx2t99", &[_]FeatureType {
.Lse,
.ArithBccFusion,
.Vh,
.Rdm,
.UsePostraScheduler,
.Crc,
.Lor,
.Pan,
.AggressiveFma,
.FpArmv8,
.Lse,
.Crc,
.Lor,
.UsePostraScheduler,
.ArithBccFusion,
.PredictableSelectExpensive,
.Thunderx2t99,
},
CpuInfo(@This()).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt81, "thunderxt81", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt81,
},
CpuInfo(@This()).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt83, "thunderxt83", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt83,
},
CpuInfo(@This()).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Thunderxt88, "thunderxt88", &[_]FeatureType {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
.Thunderxt88,
},
CpuInfo(@This()).create(.Tsv110, "tsv110", &[_]FeatureType {
.Uaops,
.Spe,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Vh,
.Perfmon,
.FpArmv8,
}),
CpuInfo(@This(), FeatureType).create(.Tsv110, "tsv110", &[_]FeatureType {
.Lse,
.Crc,
.Dotprod,
.Lor,
.Spe,
.Vh,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.CustomCheapAsMove,
.Ras,
.Ccpp,
.FpArmv8,
.FuseAes,
.Tsv110,
},
}),
};
};

1154
lib/std/target/cpu/AmdGpuCpu.zig
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File diff suppressed because it is too large Load Diff

1094
lib/std/target/cpu/ArmCpu.zig
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File diff suppressed because it is too large Load Diff

5100
lib/std/target/cpu/AvrCpu.zig
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File diff suppressed because it is too large Load Diff

28
lib/std/target/cpu/BpfCpu.zig
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@ -8,22 +8,22 @@ pub const BpfCpu = enum {
V2,
V3,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.BpfFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.BpfFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
},
CpuInfo(@This()).create(.Probe, "probe", &[_]FeatureType {
},
CpuInfo(@This()).create(.V1, "v1", &[_]FeatureType {
},
CpuInfo(@This()).create(.V2, "v2", &[_]FeatureType {
},
CpuInfo(@This()).create(.V3, "v3", &[_]FeatureType {
},
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Probe, "probe", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V1, "v1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V2, "v2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V3, "v3", &[_]FeatureType {
}),
};
};

36
lib/std/target/cpu/HexagonCpu.zig
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@ -10,14 +10,14 @@ pub const HexagonCpu = enum {
Hexagonv65,
Hexagonv66,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.HexagonFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.HexagonFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.V5,
.V55,
.V60,
@ -27,8 +27,8 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
CpuInfo(@This()).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv5, "hexagonv5", &[_]FeatureType {
.V5,
.Duplex,
.Memops,
@ -36,8 +36,8 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
CpuInfo(@This()).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv55, "hexagonv55", &[_]FeatureType {
.V5,
.V55,
.Duplex,
@ -46,8 +46,8 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
CpuInfo(@This()).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv60, "hexagonv60", &[_]FeatureType {
.V5,
.V55,
.V60,
@ -57,8 +57,8 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
CpuInfo(@This()).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv62, "hexagonv62", &[_]FeatureType {
.V5,
.V55,
.V60,
@ -69,8 +69,8 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
CpuInfo(@This()).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv65, "hexagonv65", &[_]FeatureType {
.V5,
.V55,
.V60,
@ -83,8 +83,8 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
CpuInfo(@This()).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hexagonv66, "hexagonv66", &[_]FeatureType {
.V5,
.V55,
.V60,
@ -98,6 +98,6 @@ pub const HexagonCpu = enum {
.Nvj,
.Nvs,
.SmallData,
},
}),
};
};

236
lib/std/target/cpu/MipsCpu.zig
View File

@ -20,171 +20,171 @@ pub const MipsCpu = enum {
Octeon,
P5600,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.MipsFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.MipsFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Mips1, "mips1", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Mips1, "mips1", &[_]FeatureType {
.Mips1,
},
CpuInfo(@This()).create(.Mips2, "mips2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Mips2, "mips2", &[_]FeatureType {
.Mips1,
.Mips2,
},
CpuInfo(@This()).create(.Mips3, "mips3", &[_]FeatureType {
.Mips3_32,
.Fp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips3, "mips3", &[_]FeatureType {
.Mips3_32r2,
.Mips1,
.Fp64,
.Gp64,
.Mips1,
.Mips3_32,
.Mips3,
},
CpuInfo(@This()).create(.Mips32, "mips32", &[_]FeatureType {
.Mips3_32,
}),
CpuInfo(@This(), FeatureType).create(.Mips32, "mips32", &[_]FeatureType {
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32,
},
CpuInfo(@This()).create(.Mips32r2, "mips32r2", &[_]FeatureType {
.Mips3_32,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r2, "mips32r2", &[_]FeatureType {
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips5_32r2,
.Mips1,
.Mips3_32,
.Mips32r2,
},
CpuInfo(@This()).create(.Mips32r3, "mips32r3", &[_]FeatureType {
.Mips3_32,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r3, "mips32r3", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r3,
},
CpuInfo(@This()).create(.Mips32r5, "mips32r5", &[_]FeatureType {
.Mips3_32,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r5, "mips32r5", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r5,
},
CpuInfo(@This()).create(.Mips32r6, "mips32r6", &[_]FeatureType {
.Mips3_32,
.Fp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips32r6, "mips32r6", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Abs2008,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Nan2008,
.Mips5_32r2,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips32r6,
},
CpuInfo(@This()).create(.Mips4, "mips4", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Mips4_32r2,
}),
CpuInfo(@This(), FeatureType).create(.Mips4, "mips4", &[_]FeatureType {
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips4,
},
CpuInfo(@This()).create(.Mips5, "mips5", &[_]FeatureType {
.Mips3_32,
.Fp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips5, "mips5", &[_]FeatureType {
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips5,
},
CpuInfo(@This()).create(.Mips64, "mips64", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips64, "mips64", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64,
},
CpuInfo(@This()).create(.Mips64r2, "mips64r2", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r2, "mips64r2", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r2,
},
CpuInfo(@This()).create(.Mips64r3, "mips64r3", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r3, "mips64r3", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r3,
},
CpuInfo(@This()).create(.Mips64r5, "mips64r5", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r5, "mips64r5", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r5,
},
CpuInfo(@This()).create(.Mips64r6, "mips64r6", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Abs2008,
}),
CpuInfo(@This(), FeatureType).create(.Mips64r6, "mips64r6", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Nan2008,
.Gp64,
.Mips5_32r2,
.Mips64r6,
},
CpuInfo(@This()).create(.Octeon, "octeon", &[_]FeatureType {
.Mips3_32,
.Fp64,
.Abs2008,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Mips64r6,
}),
CpuInfo(@This(), FeatureType).create(.Octeon, "octeon", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
.Cnmips,
.Mips64r2,
},
CpuInfo(@This()).create(.P5600, "p5600", &[_]FeatureType {
.Mips3_32,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
}),
CpuInfo(@This(), FeatureType).create(.P5600, "p5600", &[_]FeatureType {
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
.P5600,
},
}),
};
};

20
lib/std/target/cpu/Msp430Cpu.zig
View File

@ -6,19 +6,19 @@ pub const Msp430Cpu = enum {
Msp430,
Msp430x,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.Msp430Feature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.Msp430Feature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
},
CpuInfo(@This()).create(.Msp430, "msp430", &[_]FeatureType {
},
CpuInfo(@This()).create(.Msp430x, "msp430x", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Msp430, "msp430", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Msp430x, "msp430x", &[_]FeatureType {
.Ext,
},
}),
};
};

68
lib/std/target/cpu/NvptxCpu.zig
View File

@ -18,68 +18,68 @@ pub const NvptxCpu = enum {
Sm_72,
Sm_75,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.NvptxFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.NvptxFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Sm_20, "sm_20", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Sm_20, "sm_20", &[_]FeatureType {
.Sm_20,
},
CpuInfo(@This()).create(.Sm_21, "sm_21", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_21, "sm_21", &[_]FeatureType {
.Sm_21,
},
CpuInfo(@This()).create(.Sm_30, "sm_30", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_30, "sm_30", &[_]FeatureType {
.Sm_30,
},
CpuInfo(@This()).create(.Sm_32, "sm_32", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_32, "sm_32", &[_]FeatureType {
.Ptx40,
.Sm_32,
},
CpuInfo(@This()).create(.Sm_35, "sm_35", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_35, "sm_35", &[_]FeatureType {
.Sm_35,
},
CpuInfo(@This()).create(.Sm_37, "sm_37", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_37, "sm_37", &[_]FeatureType {
.Ptx41,
.Sm_37,
},
CpuInfo(@This()).create(.Sm_50, "sm_50", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_50, "sm_50", &[_]FeatureType {
.Ptx40,
.Sm_50,
},
CpuInfo(@This()).create(.Sm_52, "sm_52", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_52, "sm_52", &[_]FeatureType {
.Ptx41,
.Sm_52,
},
CpuInfo(@This()).create(.Sm_53, "sm_53", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_53, "sm_53", &[_]FeatureType {
.Ptx42,
.Sm_53,
},
CpuInfo(@This()).create(.Sm_60, "sm_60", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_60, "sm_60", &[_]FeatureType {
.Ptx50,
.Sm_60,
},
CpuInfo(@This()).create(.Sm_61, "sm_61", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_61, "sm_61", &[_]FeatureType {
.Ptx50,
.Sm_61,
},
CpuInfo(@This()).create(.Sm_62, "sm_62", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_62, "sm_62", &[_]FeatureType {
.Ptx50,
.Sm_62,
},
CpuInfo(@This()).create(.Sm_70, "sm_70", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_70, "sm_70", &[_]FeatureType {
.Ptx60,
.Sm_70,
},
CpuInfo(@This()).create(.Sm_72, "sm_72", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_72, "sm_72", &[_]FeatureType {
.Ptx61,
.Sm_72,
},
CpuInfo(@This()).create(.Sm_75, "sm_75", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sm_75, "sm_75", &[_]FeatureType {
.Ptx63,
.Sm_75,
},
}),
};
};

180
lib/std/target/cpu/PowerPcCpu.zig
View File

@ -2,20 +2,20 @@ const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const PowerPcCpu = enum {
440,
450,
601,
602,
603,
Cpu440,
Cpu450,
Cpu601,
Cpu602,
Cpu603,
E603,
Ev603,
604,
Cpu604,
E604,
620,
7400,
7450,
750,
970,
Cpu620,
Cpu7400,
Cpu7450,
Cpu750,
Cpu970,
A2,
A2q,
E500,
@ -23,7 +23,7 @@ pub const PowerPcCpu = enum {
E5500,
G3,
G4,
G4+,
G4plus,
G5,
Generic,
Ppc,
@ -40,14 +40,14 @@ pub const PowerPcCpu = enum {
Pwr8,
Pwr9,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.PowerPcFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.PowerPcFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.440, "440", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Cpu440, "440", &[_]FeatureType {
.Icbt,
.Booke,
.HardFloat,
@ -55,8 +55,8 @@ pub const PowerPcCpu = enum {
.Frsqrte,
.Isel,
.Msync,
},
CpuInfo(@This()).create(.450, "450", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu450, "450", &[_]FeatureType {
.Icbt,
.Booke,
.HardFloat,
@ -64,63 +64,63 @@ pub const PowerPcCpu = enum {
.Frsqrte,
.Isel,
.Msync,
},
CpuInfo(@This()).create(.601, "601", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu601, "601", &[_]FeatureType {
.HardFloat,
.Fpu,
},
CpuInfo(@This()).create(.602, "602", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu602, "602", &[_]FeatureType {
.HardFloat,
.Fpu,
},
CpuInfo(@This()).create(.603, "603", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu603, "603", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.E603, "603e", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.E603, "603e", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.Ev603, "603ev", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ev603, "603ev", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.604, "604", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu604, "604", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.E604, "604e", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.E604, "604e", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.620, "620", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu620, "620", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.7400, "7400", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu7400, "7400", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.7450, "7450", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu7450, "7450", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.750, "750", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu750, "750", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.970, "970", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cpu970, "970", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -129,8 +129,8 @@ pub const PowerPcCpu = enum {
.Fsqrt,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.A2, "a2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.A2, "a2", &[_]FeatureType {
.Bit64,
.Icbt,
.Booke,
@ -151,8 +151,8 @@ pub const PowerPcCpu = enum {
.Recipprec,
.Stfiwx,
.SlowPopcntd,
},
CpuInfo(@This()).create(.A2q, "a2q", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.A2q, "a2q", &[_]FeatureType {
.Bit64,
.Icbt,
.Booke,
@ -174,20 +174,20 @@ pub const PowerPcCpu = enum {
.Recipprec,
.Stfiwx,
.SlowPopcntd,
},
CpuInfo(@This()).create(.E500, "e500", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.E500, "e500", &[_]FeatureType {
.Icbt,
.Booke,
.Isel,
},
CpuInfo(@This()).create(.E500mc, "e500mc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.E500mc, "e500mc", &[_]FeatureType {
.Icbt,
.Booke,
.Isel,
.HardFloat,
.Stfiwx,
},
CpuInfo(@This()).create(.E5500, "e5500", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.E5500, "e5500", &[_]FeatureType {
.Bit64,
.Icbt,
.Booke,
@ -195,25 +195,25 @@ pub const PowerPcCpu = enum {
.Mfocrf,
.HardFloat,
.Stfiwx,
},
CpuInfo(@This()).create(.G3, "g3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.G3, "g3", &[_]FeatureType {
.HardFloat,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.G4, "g4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.G4, "g4", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.G4+, "g4+", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.G4plus, "g4+", &[_]FeatureType {
.HardFloat,
.Altivec,
.Fres,
.Frsqrte,
},
CpuInfo(@This()).create(.G5, "g5", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.G5, "g5", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -222,17 +222,17 @@ pub const PowerPcCpu = enum {
.Fsqrt,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.HardFloat,
},
CpuInfo(@This()).create(.Ppc, "ppc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ppc, "ppc", &[_]FeatureType {
.HardFloat,
},
CpuInfo(@This()).create(.Ppc32, "ppc32", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ppc32, "ppc32", &[_]FeatureType {
.HardFloat,
},
CpuInfo(@This()).create(.Ppc64, "ppc64", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ppc64, "ppc64", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -241,8 +241,8 @@ pub const PowerPcCpu = enum {
.Fsqrt,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.Ppc64le, "ppc64le", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ppc64le, "ppc64le", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -273,8 +273,8 @@ pub const PowerPcCpu = enum {
.Stfiwx,
.TwoConstNr,
.Vsx,
},
CpuInfo(@This()).create(.Pwr3, "pwr3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr3, "pwr3", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -282,8 +282,8 @@ pub const PowerPcCpu = enum {
.Frsqrte,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.Pwr4, "pwr4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr4, "pwr4", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -292,8 +292,8 @@ pub const PowerPcCpu = enum {
.Fsqrt,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.Pwr5, "pwr5", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr5, "pwr5", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -304,8 +304,8 @@ pub const PowerPcCpu = enum {
.Fsqrt,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.Pwr5x, "pwr5x", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr5x, "pwr5x", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -317,8 +317,8 @@ pub const PowerPcCpu = enum {
.Fsqrt,
.Mfocrf,
.Stfiwx,
},
CpuInfo(@This()).create(.Pwr6, "pwr6", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr6, "pwr6", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -334,8 +334,8 @@ pub const PowerPcCpu = enum {
.Mfocrf,
.Recipprec,
.Stfiwx,
},
CpuInfo(@This()).create(.Pwr6x, "pwr6x", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr6x, "pwr6x", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -351,8 +351,8 @@ pub const PowerPcCpu = enum {
.Mfocrf,
.Recipprec,
.Stfiwx,
},
CpuInfo(@This()).create(.Pwr7, "pwr7", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr7, "pwr7", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -376,8 +376,8 @@ pub const PowerPcCpu = enum {
.Stfiwx,
.TwoConstNr,
.Vsx,
},
CpuInfo(@This()).create(.Pwr8, "pwr8", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr8, "pwr8", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -408,8 +408,8 @@ pub const PowerPcCpu = enum {
.Stfiwx,
.TwoConstNr,
.Vsx,
},
CpuInfo(@This()).create(.Pwr9, "pwr9", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pwr9, "pwr9", &[_]FeatureType {
.Bit64,
.HardFloat,
.Altivec,
@ -446,6 +446,6 @@ pub const PowerPcCpu = enum {
.TwoConstNr,
.Vsx,
.VectorsUseTwoUnits,
},
}),
};
};

16
lib/std/target/cpu/RiscVCpu.zig
View File

@ -5,19 +5,19 @@ pub const RiscVCpu = enum {
GenericRv32,
GenericRv64,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.RiscVFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.RiscVFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.GenericRv32, "generic-rv32", &[_]FeatureType {
.RvcHints,
},
CpuInfo(@This()).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.GenericRv64, "generic-rv64", &[_]FeatureType {
.Bit64,
.RvcHints,
},
}),
};
};

168
lib/std/target/cpu/SparcCpu.zig
View File

@ -43,174 +43,174 @@ pub const SparcCpu = enum {
V8,
V9,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.SparcFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.SparcFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.At697e, "at697e", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.At697e, "at697e", &[_]FeatureType {
.Leon,
.Insertnopload,
},
CpuInfo(@This()).create(.At697f, "at697f", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.At697f, "at697f", &[_]FeatureType {
.Leon,
.Insertnopload,
},
CpuInfo(@This()).create(.F934, "f934", &[_]FeatureType {
},
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
},
CpuInfo(@This()).create(.Gr712rc, "gr712rc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.F934, "f934", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Gr712rc, "gr712rc", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Gr740, "gr740", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Gr740, "gr740", &[_]FeatureType {
.Leon,
.Leonpwrpsr,
.Hasleoncasa,
.Leoncyclecounter,
.Hasumacsmac,
},
CpuInfo(@This()).create(.Hypersparc, "hypersparc", &[_]FeatureType {
},
CpuInfo(@This()).create(.Leon2, "leon2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Hypersparc, "hypersparc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Leon2, "leon2", &[_]FeatureType {
.Leon,
},
CpuInfo(@This()).create(.Leon3, "leon3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Leon3, "leon3", &[_]FeatureType {
.Leon,
.Hasumacsmac,
},
CpuInfo(@This()).create(.Leon4, "leon4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Leon4, "leon4", &[_]FeatureType {
.Leon,
.Hasleoncasa,
.Hasumacsmac,
},
CpuInfo(@This()).create(.Ma2080, "ma2080", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2080, "ma2080", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2085, "ma2085", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2085, "ma2085", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2100, "ma2100", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2100, "ma2100", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2150, "ma2150", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2150, "ma2150", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2155, "ma2155", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2155, "ma2155", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2450, "ma2450", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2450, "ma2450", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2455, "ma2455", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2455, "ma2455", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2480, "ma2480", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2480, "ma2480", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2485, "ma2485", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2485, "ma2485", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2x5x, "ma2x5x", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ma2x8x, "ma2x8x", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Myriad2, "myriad2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Myriad2, "myriad2", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Myriad21, "myriad2.1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Myriad21, "myriad2.1", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Myriad22, "myriad2.2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Myriad22, "myriad2.2", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Myriad23, "myriad2.3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Myriad23, "myriad2.3", &[_]FeatureType {
.Leon,
.Hasleoncasa,
},
CpuInfo(@This()).create(.Niagara, "niagara", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Niagara, "niagara", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
},
CpuInfo(@This()).create(.Niagara2, "niagara2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Niagara2, "niagara2", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
.Popc,
},
CpuInfo(@This()).create(.Niagara3, "niagara3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Niagara3, "niagara3", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
.Popc,
},
CpuInfo(@This()).create(.Niagara4, "niagara4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Niagara4, "niagara4", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
.Vis3,
.Popc,
},
CpuInfo(@This()).create(.Sparclet, "sparclet", &[_]FeatureType {
},
CpuInfo(@This()).create(.Sparclite, "sparclite", &[_]FeatureType {
},
CpuInfo(@This()).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
},
CpuInfo(@This()).create(.Supersparc, "supersparc", &[_]FeatureType {
},
CpuInfo(@This()).create(.Tsc701, "tsc701", &[_]FeatureType {
},
CpuInfo(@This()).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sparclet, "sparclet", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sparclite, "sparclite", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sparclite86x, "sparclite86x", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Supersparc, "supersparc", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Tsc701, "tsc701", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ultrasparc, "ultrasparc", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
},
CpuInfo(@This()).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ultrasparc3, "ultrasparc3", &[_]FeatureType {
.DeprecatedV8,
.V9,
.Vis,
.Vis2,
},
CpuInfo(@This()).create(.Ut699, "ut699", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ut699, "ut699", &[_]FeatureType {
.Leon,
.NoFmuls,
.NoFsmuld,
.Fixallfdivsqrt,
.Insertnopload,
},
CpuInfo(@This()).create(.V7, "v7", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V7, "v7", &[_]FeatureType {
.NoFsmuld,
.SoftMulDiv,
},
CpuInfo(@This()).create(.V8, "v8", &[_]FeatureType {
},
CpuInfo(@This()).create(.V9, "v9", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V8, "v8", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.V9, "v9", &[_]FeatureType {
.V9,
},
}),
};
};

60
lib/std/target/cpu/SystemZCpu.zig
View File

@ -16,14 +16,14 @@ pub const SystemZCpu = enum {
Z196,
ZEC12,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.SystemZFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.SystemZFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Arch10, "arch10", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Arch10, "arch10", &[_]FeatureType {
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
@ -41,8 +41,8 @@ pub const SystemZCpu = enum {
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
},
CpuInfo(@This()).create(.Arch11, "arch11", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Arch11, "arch11", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
@ -65,8 +65,8 @@ pub const SystemZCpu = enum {
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
},
CpuInfo(@This()).create(.Arch12, "arch12", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Arch12, "arch12", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
@ -96,8 +96,8 @@ pub const SystemZCpu = enum {
.Vector,
.VectorEnhancements1,
.VectorPackedDecimal,
},
CpuInfo(@This()).create(.Arch13, "arch13", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Arch13, "arch13", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DeflateConversion,
@ -133,10 +133,10 @@ pub const SystemZCpu = enum {
.VectorEnhancements2,
.VectorPackedDecimal,
.VectorPackedDecimalEnhancement,
},
CpuInfo(@This()).create(.Arch8, "arch8", &[_]FeatureType {
},
CpuInfo(@This()).create(.Arch9, "arch9", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Arch8, "arch8", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Arch9, "arch9", &[_]FeatureType {
.DistinctOps,
.FpExtension,
.FastSerialization,
@ -147,12 +147,12 @@ pub const SystemZCpu = enum {
.MessageSecurityAssistExtension4,
.PopulationCount,
.ResetReferenceBitsMultiple,
},
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
},
CpuInfo(@This()).create(.Z10, "z10", &[_]FeatureType {
},
CpuInfo(@This()).create(.Z13, "z13", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z10, "z10", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z13, "z13", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
@ -175,8 +175,8 @@ pub const SystemZCpu = enum {
.ResetReferenceBitsMultiple,
.TransactionalExecution,
.Vector,
},
CpuInfo(@This()).create(.Z14, "z14", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z14, "z14", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DistinctOps,
@ -206,8 +206,8 @@ pub const SystemZCpu = enum {
.Vector,
.VectorEnhancements1,
.VectorPackedDecimal,
},
CpuInfo(@This()).create(.Z15, "z15", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z15, "z15", &[_]FeatureType {
.DfpPackedConversion,
.DfpZonedConversion,
.DeflateConversion,
@ -243,8 +243,8 @@ pub const SystemZCpu = enum {
.VectorEnhancements2,
.VectorPackedDecimal,
.VectorPackedDecimalEnhancement,
},
CpuInfo(@This()).create(.Z196, "z196", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Z196, "z196", &[_]FeatureType {
.DistinctOps,
.FpExtension,
.FastSerialization,
@ -255,8 +255,8 @@ pub const SystemZCpu = enum {
.MessageSecurityAssistExtension4,
.PopulationCount,
.ResetReferenceBitsMultiple,
},
CpuInfo(@This()).create(.ZEC12, "zEC12", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.ZEC12, "zEC12", &[_]FeatureType {
.DfpZonedConversion,
.DistinctOps,
.EnhancedDat2,
@ -274,6 +274,6 @@ pub const SystemZCpu = enum {
.ProcessorAssist,
.ResetReferenceBitsMultiple,
.TransactionalExecution,
},
}),
};
};

20
lib/std/target/cpu/WebAssemblyCpu.zig
View File

@ -6,23 +6,23 @@ pub const WebAssemblyCpu = enum {
Generic,
Mvp,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.WebAssemblyFeature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.WebAssemblyFeature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.BleedingEdge, "bleeding-edge", &[_]FeatureType {
.Atomics,
.MutableGlobals,
.NontrappingFptoint,
.Simd128,
.SignExt,
},
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
},
CpuInfo(@This()).create(.Mvp, "mvp", &[_]FeatureType {
},
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Mvp, "mvp", &[_]FeatureType {
}),
};
};

324
lib/std/target/cpu/X86Cpu.zig
View File

@ -82,14 +82,14 @@ pub const X86Cpu = enum {
Znver1,
Znver2,
pub fn getInfo(self: @This()) CpuInfo {
const FeatureType = feature.X86Feature;
pub fn getInfo(self: @This()) CpuInfo(@This(), FeatureType) {
return cpu_infos[@enumToInt(self)];
}
pub const FeatureType = feature.X86Feature;
const cpu_infos = [@memberCount(@This())]CpuInfo(@This()) {
CpuInfo(@This()).create(.Amdfam10, "amdfam10", &[_]FeatureType {
pub const cpu_infos = [@memberCount(@This())]CpuInfo(@This(), FeatureType) {
CpuInfo(@This(), FeatureType).create(.Amdfam10, "amdfam10", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -106,8 +106,8 @@ pub const X86Cpu = enum {
.Sse4a,
.SlowShld,
.X87,
},
CpuInfo(@This()).create(.Athlon, "athlon", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Athlon, "athlon", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Cmov,
@ -116,8 +116,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Athlon4, "athlon-4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Athlon4, "athlon-4", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Cmov,
@ -128,8 +128,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.AthlonFx, "athlon-fx", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -143,8 +143,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.AthlonMp, "athlon-mp", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Cmov,
@ -155,8 +155,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.AthlonTbird, "athlon-tbird", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Cmov,
@ -165,8 +165,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.AthlonXp, "athlon-xp", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Cmov,
@ -177,8 +177,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Athlon64, "athlon64", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Athlon64, "athlon64", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -192,8 +192,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Athlon64Sse3, "athlon64-sse3", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -208,8 +208,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Atom, "atom", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Atom, "atom", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -229,8 +229,8 @@ pub const X86Cpu = enum {
.SlowTwoMemOps,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Barcelona, "barcelona", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Barcelona, "barcelona", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -247,8 +247,8 @@ pub const X86Cpu = enum {
.Sse4a,
.SlowShld,
.X87,
},
CpuInfo(@This()).create(.Bdver1, "bdver1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Bdver1, "bdver1", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -271,8 +271,8 @@ pub const X86Cpu = enum {
.X87,
.Xop,
.Xsave,
},
CpuInfo(@This()).create(.Bdver2, "bdver2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Bdver2, "bdver2", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -300,8 +300,8 @@ pub const X86Cpu = enum {
.X87,
.Xop,
.Xsave,
},
CpuInfo(@This()).create(.Bdver3, "bdver3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Bdver3, "bdver3", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -331,8 +331,8 @@ pub const X86Cpu = enum {
.Xop,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Bdver4, "bdver4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Bdver4, "bdver4", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -365,8 +365,8 @@ pub const X86Cpu = enum {
.Xop,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Bonnell, "bonnell", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Bonnell, "bonnell", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -386,8 +386,8 @@ pub const X86Cpu = enum {
.SlowTwoMemOps,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Broadwell, "broadwell", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Broadwell, "broadwell", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -427,8 +427,8 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Btver1, "btver1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Btver1, "btver1", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -448,8 +448,8 @@ pub const X86Cpu = enum {
.Ssse3,
.SlowShld,
.X87,
},
CpuInfo(@This()).create(.Btver2, "btver2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Btver2, "btver2", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -481,14 +481,14 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.C3, "c3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.C3, "c3", &[_]FeatureType {
.Mmx,
.Dnow3,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.C32, "c3-2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.C32, "c3-2", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -496,8 +496,8 @@ pub const X86Cpu = enum {
.Sse,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Cannonlake, "cannonlake", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cannonlake, "cannonlake", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -552,8 +552,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Cascadelake, "cascadelake", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cascadelake, "cascadelake", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -607,8 +607,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Cooperlake, "cooperlake", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Cooperlake, "cooperlake", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -663,8 +663,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CoreAvxI, "core-avx-i", &[_]FeatureType {
.Bit64,
.Sse,
.Avx,
@ -692,8 +692,8 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.CoreAvx2, "core-avx2", &[_]FeatureType {
.Bit64,
.Sse,
.Avx,
@ -730,8 +730,8 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Core2, "core2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Core2, "core2", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -745,8 +745,8 @@ pub const X86Cpu = enum {
.Ssse3,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Corei7, "corei7", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Corei7, "corei7", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -760,8 +760,8 @@ pub const X86Cpu = enum {
.Sse,
.Sse42,
.X87,
},
CpuInfo(@This()).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Corei7Avx, "corei7-avx", &[_]FeatureType {
.Bit64,
.Sse,
.Avx,
@ -786,20 +786,20 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Generic, "generic", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Generic, "generic", &[_]FeatureType {
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Geode, "geode", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Geode, "geode", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Goldmont, "goldmont", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Goldmont, "goldmont", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -830,8 +830,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.GoldmontPlus, "goldmont-plus", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -864,8 +864,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Haswell, "haswell", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Haswell, "haswell", &[_]FeatureType {
.Bit64,
.Sse,
.Avx,
@ -902,27 +902,27 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.I386, "i386", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.I386, "i386", &[_]FeatureType {
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.I486, "i486", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.I486, "i486", &[_]FeatureType {
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.I586, "i586", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.I586, "i586", &[_]FeatureType {
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.I686, "i686", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.I686, "i686", &[_]FeatureType {
.Cmov,
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.IcelakeClient, "icelake-client", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -986,8 +986,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.IcelakeServer, "icelake-server", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1053,8 +1053,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Ivybridge, "ivybridge", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Ivybridge, "ivybridge", &[_]FeatureType {
.Bit64,
.Sse,
.Avx,
@ -1082,28 +1082,28 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.K6, "k6", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.K6, "k6", &[_]FeatureType {
.Cx8,
.Mmx,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.K62, "k6-2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.K62, "k6-2", &[_]FeatureType {
.Mmx,
.Dnow3,
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.K63, "k6-3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.K63, "k6-3", &[_]FeatureType {
.Mmx,
.Dnow3,
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.K8, "k8", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.K8, "k8", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -1117,8 +1117,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.K8Sse3, "k8-sse3", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -1133,8 +1133,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Knl, "knl", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Knl, "knl", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1173,8 +1173,8 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Knm, "knm", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Knm, "knm", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1214,10 +1214,10 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Lakemont, "lakemont", &[_]FeatureType {
},
CpuInfo(@This()).create(.Nehalem, "nehalem", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Lakemont, "lakemont", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Nehalem, "nehalem", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1231,8 +1231,8 @@ pub const X86Cpu = enum {
.Sse,
.Sse42,
.X87,
},
CpuInfo(@This()).create(.Nocona, "nocona", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Nocona, "nocona", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1244,8 +1244,8 @@ pub const X86Cpu = enum {
.Sse3,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Opteron, "opteron", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Opteron, "opteron", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -1259,8 +1259,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.OpteronSse3, "opteron-sse3", &[_]FeatureType {
.Mmx,
.Dnowa3,
.Bit64,
@ -1275,8 +1275,8 @@ pub const X86Cpu = enum {
.SlowShld,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Penryn, "penryn", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Penryn, "penryn", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1290,13 +1290,13 @@ pub const X86Cpu = enum {
.Sse41,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentium, "pentium", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentium, "pentium", &[_]FeatureType {
.Cx8,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.PentiumM, "pentium-m", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.PentiumM, "pentium-m", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1306,14 +1306,14 @@ pub const X86Cpu = enum {
.Sse2,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.PentiumMmx, "pentium-mmx", &[_]FeatureType {
.Cx8,
.Mmx,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentium2, "pentium2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentium2, "pentium2", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1321,8 +1321,8 @@ pub const X86Cpu = enum {
.Nopl,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentium3, "pentium3", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentium3, "pentium3", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1331,8 +1331,8 @@ pub const X86Cpu = enum {
.Sse,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentium3m, "pentium3m", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentium3m, "pentium3m", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1341,8 +1341,8 @@ pub const X86Cpu = enum {
.Sse,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentium4, "pentium4", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentium4, "pentium4", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1352,8 +1352,8 @@ pub const X86Cpu = enum {
.Sse2,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentium4m, "pentium4m", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentium4m, "pentium4m", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1363,15 +1363,15 @@ pub const X86Cpu = enum {
.Sse2,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Pentiumpro, "pentiumpro", &[_]FeatureType {
.Cmov,
.Cx8,
.Nopl,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Prescott, "prescott", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Prescott, "prescott", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1381,8 +1381,8 @@ pub const X86Cpu = enum {
.Sse3,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Sandybridge, "sandybridge", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Sandybridge, "sandybridge", &[_]FeatureType {
.Bit64,
.Sse,
.Avx,
@ -1407,8 +1407,8 @@ pub const X86Cpu = enum {
.X87,
.Xsave,
.Xsaveopt,
},
CpuInfo(@This()).create(.Silvermont, "silvermont", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Silvermont, "silvermont", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1432,8 +1432,8 @@ pub const X86Cpu = enum {
.SlowPmulld,
.SlowTwoMemOps,
.X87,
},
CpuInfo(@This()).create(.Skx, "skx", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Skx, "skx", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1486,8 +1486,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Skylake, "skylake", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Skylake, "skylake", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1533,8 +1533,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.SkylakeAvx512, "skylake-avx512", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1587,8 +1587,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Slm, "slm", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Slm, "slm", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1612,8 +1612,8 @@ pub const X86Cpu = enum {
.SlowPmulld,
.SlowTwoMemOps,
.X87,
},
CpuInfo(@This()).create(.Tigerlake, "tigerlake", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Tigerlake, "tigerlake", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1681,8 +1681,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Tremont, "tremont", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Tremont, "tremont", &[_]FeatureType {
.Bit64,
.Sse,
.Aes,
@ -1720,8 +1720,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Westmere, "westmere", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Westmere, "westmere", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1736,19 +1736,19 @@ pub const X86Cpu = enum {
.Popcnt,
.Sse42,
.X87,
},
CpuInfo(@This()).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.WinchipC6, "winchip-c6", &[_]FeatureType {
.Mmx,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Winchip2, "winchip2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Winchip2, "winchip2", &[_]FeatureType {
.Mmx,
.Dnow3,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.X8664, "x86-64", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.X8664, "x86-64", &[_]FeatureType {
.Bit64,
.Cmov,
.Cx8,
@ -1761,8 +1761,8 @@ pub const X86Cpu = enum {
.Slow3opsLea,
.SlowIncdec,
.X87,
},
CpuInfo(@This()).create(.Yonah, "yonah", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Yonah, "yonah", &[_]FeatureType {
.Cmov,
.Cx8,
.Fxsr,
@ -1772,8 +1772,8 @@ pub const X86Cpu = enum {
.Sse3,
.SlowUnalignedMem16,
.X87,
},
CpuInfo(@This()).create(.Znver1, "znver1", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Znver1, "znver1", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1814,8 +1814,8 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
CpuInfo(@This()).create(.Znver2, "znver2", &[_]FeatureType {
}),
CpuInfo(@This(), FeatureType).create(.Znver2, "znver2", &[_]FeatureType {
.Bit64,
.Adx,
.Sse,
@ -1859,6 +1859,6 @@ pub const X86Cpu = enum {
.Xsavec,
.Xsaveopt,
.Xsaves,
},
}),
};
};

4
lib/std/target/cpu/empty.zig
View File

@ -1,6 +1,6 @@
const feature = @import("std").target.feature;
const CpuInfo = @import("std").target.cpu.CpuInfo;
pub const EmptyCpu = enum {
pub const cpu_infos = [0]CpuInfo(@This()) {};
pub const EmptyCpu = struct {
pub const cpu_infos = [0]CpuInfo(@This(), feature.EmptyFeature) {};
};

12
lib/std/target/feature.zig
View File

@ -17,7 +17,7 @@ pub const SystemZFeature = @import("feature/SystemZFeature.zig").SystemZFeature;
pub const WebAssemblyFeature = @import("feature/WebAssemblyFeature.zig").WebAssemblyFeature;
pub const X86Feature = @import("feature/X86Feature.zig").X86Feature;
const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
pub const EmptyFeature = @import("feature/empty.zig").EmptyFeature;
pub fn ArchFeature(comptime arch: @TagType(Arch)) type {
return switch (arch) {
@ -49,24 +49,30 @@ pub fn FeatureInfo(comptime EnumType: type) type {
return struct {
value: EnumType,
name: []const u8,
description: []const u8,
llvm_name: []const u8,
subfeatures: []const EnumType,
const Self = @This();
fn create(value: EnumType, name: []const u8) Self {
pub fn create(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8) Self {
return Self {
.value = value,
.name = name,
.description = description,
.llvm_name = llvm_name,
.subfeatures = &[_]EnumType{},
};
}
fn createWithSubfeatures(value: EnumType, name: []const u8, subfeatures: []const EnumType) Self {
pub fn createWithSubfeatures(value: EnumType, name: []const u8, description: []const u8, llvm_name: []const u8, subfeatures: []const EnumType) Self {
return Self {
.value = value,
.name = name,
.description = description,
.llvm_name = llvm_name,
.subfeatures = subfeatures,
};

492
lib/std/target/feature/AArch64Feature.zig
View File

@ -155,7 +155,7 @@ pub const AArch64Feature = enum {
Thunderxt83,
Thunderxt88,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
@ -291,19 +291,19 @@ pub const AArch64Feature = enum {
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Aes, "sve2-aes", "Enable AES SVE2 instructions", "sve2-aes", &[_]@This() {
.Sve,
.FpArmv8,
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Bitperm, "sve2-bitperm", "Enable bit permutation SVE2 instructions", "sve2-bitperm", &[_]@This() {
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Sha3, "sve2-sha3", "Enable SHA3 SVE2 instructions", "sve2-sha3", &[_]@This() {
.Sve,
.FpArmv8,
.Sve,
}),
FeatureInfo(@This()).createWithSubfeatures(.Sve2Sm4, "sve2-sm4", "Enable SM4 SVE2 instructions", "sve2-sm4", &[_]@This() {
.Sve,
.FpArmv8,
.Sve,
}),
FeatureInfo(@This()).create(.SlowMisaligned128store, "slow-misaligned-128store", "Misaligned 128 bit stores are slow", "slow-misaligned-128store"),
FeatureInfo(@This()).create(.SlowPaired128, "slow-paired-128", "Paired 128 bit loads and stores are slow", "slow-paired-128"),
@ -323,101 +323,101 @@ pub const AArch64Feature = enum {
FeatureInfo(@This()).create(.Vh, "vh", "Enables ARM v8.1 Virtual Host extension", "vh"),
FeatureInfo(@This()).create(.Zcm, "zcm", "Has zero-cycle register moves", "zcm"),
FeatureInfo(@This()).createWithSubfeatures(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz", &[_]@This() {
.ZczFp,
.ZczGp,
.ZczFp,
}),
FeatureInfo(@This()).create(.ZczFp, "zcz-fp", "Has zero-cycle zeroing instructions for FP registers", "zcz-fp"),
FeatureInfo(@This()).create(.ZczFpWorkaround, "zcz-fp-workaround", "The zero-cycle floating-point zeroing instruction has a bug", "zcz-fp-workaround"),
FeatureInfo(@This()).create(.ZczGp, "zcz-gp", "Has zero-cycle zeroing instructions for generic registers", "zcz-gp"),
FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
.Pan,
.Rdm,
.Lse,
.Rdm,
.Crc,
.Lor,
.Pan,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
.Ccpp,
.Pan,
.Rdm,
.Lse,
.Rdm,
.Pan,
.Crc,
.Lor,
.Uaops,
.Vh,
.Ras,
.Ccpp,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Ccidx,
.Vh,
.Pa,
.Rdm,
.Pan,
.Crc,
.Lor,
.Pa,
.Uaops,
.Vh,
.Ras,
.Rcpc,
.Ccpp,
.Ccidx,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
.Nv,
.Am,
.Lse,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.Ccpp,
.TlbRmi,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.Pa,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.FpArmv8,
.Ccidx,
.Lse,
.Nv,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.FpArmv8,
.Crc,
.Fmi,
.Vh,
}),
FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
.Nv,
.Vh,
.Rdm,
.Dit,
.Am,
.Lse,
.Fptoint,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.Sb,
.Ccpp,
.Ssbs,
.Specrestrict,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Bti,
.Ccdp,
.TlbRmi,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.Pa,
.Ssbs,
.Dit,
.Ras,
.Uaops,
.Tracev84,
.Mpam,
.Lse,
.Sb,
.Nv,
.Altnzcv,
.FpArmv8,
.Ccidx,
.Dotprod,
.Crc,
.TlbRmi,
.Lor,
.Ccidx,
.Predres,
.Vh,
.Crc,
.Fptoint,
.Fmi,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.A35, "a35", "Cortex-A35 ARM processors", "a35", &[_]@This() {
.Perfmon,
@ -425,325 +425,325 @@ pub const AArch64Feature = enum {
.Crc,
}),
FeatureInfo(@This()).createWithSubfeatures(.A53, "a53", "Cortex-A53 ARM processors", "a53", &[_]@This() {
.UseAa,
.FuseAes,
.FpArmv8,
.Perfmon,
.Crc,
.BalanceFpOps,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.BalanceFpOps,
.UseAa,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A55, "a55", "Cortex-A55 ARM processors", "a55", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Perfmon,
.FpArmv8,
.Lse,
.Crc,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Vh,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A57, "a57", "Cortex-A57 ARM processors", "a57", &[_]@This() {
.FuseLiterals,
.FuseAes,
.FpArmv8,
.Perfmon,
.Crc,
.BalanceFpOps,
.UsePostraScheduler,
.CustomCheapAsMove,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.BalanceFpOps,
.FuseLiterals,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A65, "a65", "Cortex-A65 ARM processors", "a65", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.A72, "a72", "Cortex-A72 ARM processors", "a72", &[_]@This() {
.Perfmon,
.FuseAes,
.FpArmv8,
.Crc,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A73, "a73", "Cortex-A73 ARM processors", "a73", &[_]@This() {
.Perfmon,
.FuseAes,
.FpArmv8,
.Crc,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A75, "a75", "Cortex-A75 ARM processors", "a75", &[_]@This() {
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Perfmon,
.FpArmv8,
.Lse,
.Crc,
.Vh,
.Rdm,
.Perfmon,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.Vh,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.A76, "a76", "Cortex-A76 ARM processors", "a76", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.Cyclone, "cyclone", "Cyclone", "cyclone", &[_]@This() {
.ZczFp,
.ArithCbzFusion,
.FuseAes,
.AlternateSextloadCvtF32Pattern,
.ZczFpWorkaround,
.FpArmv8,
.Perfmon,
.DisableLatencySchedHeuristic,
.Zcm,
.ZczGp,
.ArithBccFusion,
.ArithCbzFusion,
.ZczFp,
.AlternateSextloadCvtF32Pattern,
.DisableLatencySchedHeuristic,
.Perfmon,
.ZczGp,
.ZczFpWorkaround,
.Zcm,
.FpArmv8,
.FuseCryptoEor,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm1, "exynosm1", "Samsung Exynos-M1 processors", "exynosm1", &[_]@This() {
.ZczFp,
.FuseAes,
.SlowPaired128,
.Force32bitJumpTables,
.UseReciprocalSquareRoot,
.FpArmv8,
.Perfmon,
.SlowMisaligned128store,
.Crc,
.UsePostraScheduler,
.Crc,
.UseReciprocalSquareRoot,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm2, "exynosm2", "Samsung Exynos-M2 processors", "exynosm2", &[_]@This() {
.ZczFp,
.FuseAes,
.SlowPaired128,
.Force32bitJumpTables,
.FpArmv8,
.Perfmon,
.SlowMisaligned128store,
.Crc,
.UsePostraScheduler,
.Crc,
.CustomCheapAsMove,
.Force32bitJumpTables,
.SlowMisaligned128store,
.FpArmv8,
.SlowPaired128,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm3, "exynosm3", "Samsung Exynos-M3 processors", "exynosm3", &[_]@This() {
.ZczFp,
.FuseLiterals,
.FuseAes,
.Force32bitJumpTables,
.FpArmv8,
.Perfmon,
.Crc,
.LslFast,
.FuseAddress,
.UsePostraScheduler,
.CustomCheapAsMove,
.PredictableSelectExpensive,
.FuseCsel,
.ZczFp,
.Perfmon,
.UsePostraScheduler,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.Force32bitJumpTables,
.FuseLiterals,
.FuseAddress,
.LslFast,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Exynosm4, "exynosm4", "Samsung Exynos-M4 processors", "exynosm4", &[_]@This() {
.ZczFp,
.Lse,
.FuseArithLogic,
.Lor,
.UsePostraScheduler,
.Uaops,
.CustomCheapAsMove,
.ArithBccFusion,
.Ccpp,
.Perfmon,
.Pan,
.Vh,
.ArithCbzFusion,
.ZczFp,
.Rdm,
.FuseLiterals,
.UsePostraScheduler,
.Ras,
.Force32bitJumpTables,
.Ccpp,
.FuseCsel,
.Pan,
.Uaops,
.FuseLiterals,
.LslFast,
.Lse,
.Perfmon,
.Dotprod,
.Lor,
.FuseArithLogic,
.Crc,
.CustomCheapAsMove,
.FuseAddress,
.ZczGp,
.Ras,
.FuseCsel,
.ArithCbzFusion,
.FuseAes,
.FpArmv8,
.Crc,
.Dotprod,
.Vh,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Falkor, "falkor", "Qualcomm Falkor processors", "falkor", &[_]@This() {
.ZczFp,
.Rdm,
.SlowStrqroStore,
.Perfmon,
.FpArmv8,
.Crc,
.LslFast,
.UsePostraScheduler,
.ZczGp,
.CustomCheapAsMove,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.SlowStrqroStore,
.LslFast,
}),
FeatureInfo(@This()).createWithSubfeatures(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo", &[_]@This() {
.ZczFp,
.Perfmon,
.FpArmv8,
.Crc,
.LslFast,
.UsePostraScheduler,
.ZczGp,
.CustomCheapAsMove,
.Crc,
.PredictableSelectExpensive,
.CustomCheapAsMove,
.ZczGp,
.FpArmv8,
.LslFast,
}),
FeatureInfo(@This()).createWithSubfeatures(.Neoversee1, "neoversee1", "Neoverse E1 ARM processors", "neoversee1", &[_]@This() {
.Lse,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Vh,
.Ras,
}),
FeatureInfo(@This()).createWithSubfeatures(.Neoversen1, "neoversen1", "Neoverse N1 ARM processors", "neoversen1", &[_]@This() {
.Rcpc,
.Spe,
.Ccpp,
.Pan,
.Rdm,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Ssbs,
.Uaops,
.Spe,
.Vh,
.Rdm,
.Pan,
.Dotprod,
.Crc,
.Ssbs,
.Lor,
.Uaops,
.Ras,
.Rcpc,
.Ccpp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Saphira, "saphira", "Qualcomm Saphira processors", "saphira", &[_]@This() {
.ZczFp,
.Nv,
.Am,
.Lse,
.Sel2,
.Lor,
.Tracev84,
.Uaops,
.UsePostraScheduler,
.CustomCheapAsMove,
.Ccpp,
.Perfmon,
.TlbRmi,
.PredictableSelectExpensive,
.Fmi,
.Rcpc,
.Pan,
.Rdm,
.LslFast,
.Pa,
.ZczGp,
.Dit,
.Ras,
.Spe,
.Mpam,
.FpArmv8,
.Ccidx,
.Dotprod,
.Crc,
.Vh,
.ZczFp,
.Rdm,
.UsePostraScheduler,
.Dit,
.Am,
.Ras,
.Rcpc,
.Sel2,
.Ccpp,
.Pa,
.Pan,
.Uaops,
.Tracev84,
.Mpam,
.LslFast,
.Lse,
.Nv,
.Perfmon,
.Dotprod,
.TlbRmi,
.Lor,
.Ccidx,
.PredictableSelectExpensive,
.Crc,
.CustomCheapAsMove,
.Fmi,
.ZczGp,
.FpArmv8,
}),
FeatureInfo(@This()).createWithSubfeatures(.Tsv110, "tsv110", "HiSilicon TS-V110 processors", "tsv110", &[_]@This() {
.Uaops,
.Spe,
.Ccpp,
.Pan,
.Rdm,
.FuseAes,
.Vh,
.Perfmon,
.FpArmv8,
.Lse,
.Crc,
.Dotprod,
.Lor,
.Spe,
.Vh,
.Rdm,
.Perfmon,
.UsePostraScheduler,
.Pan,
.Dotprod,
.Crc,
.Lor,
.Uaops,
.CustomCheapAsMove,
.Ras,
.Ccpp,
.FpArmv8,
.FuseAes,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderx, "thunderx", "Cavium ThunderX processors", "thunderx", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderx2t99, "thunderx2t99", "Cavium ThunderX2 processors", "thunderx2t99", &[_]@This() {
.Pan,
.Rdm,
.Vh,
.AggressiveFma,
.FpArmv8,
.Lse,
.ArithBccFusion,
.Vh,
.Rdm,
.UsePostraScheduler,
.Crc,
.Lor,
.UsePostraScheduler,
.ArithBccFusion,
.Pan,
.AggressiveFma,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt81, "thunderxt81", "Cavium ThunderX processors", "thunderxt81", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt83, "thunderxt83", "Cavium ThunderX processors", "thunderxt83", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
FeatureInfo(@This()).createWithSubfeatures(.Thunderxt88, "thunderxt88", "Cavium ThunderX processors", "thunderxt88", &[_]@This() {
.Perfmon,
.FpArmv8,
.Crc,
.UsePostraScheduler,
.Crc,
.FpArmv8,
.PredictableSelectExpensive,
}),
};

162
lib/std/target/feature/AmdGpuFeature.zig
View File

@ -110,7 +110,7 @@ pub const AmdGpuFeature = enum {
Xnack,
HalfRate64Ops,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
@ -166,73 +166,73 @@ pub const AmdGpuFeature = enum {
FeatureInfo(@This()).create(.Gfx7Gfx8Gfx9Insts, "gfx7-gfx8-gfx9-insts", "Instructions shared in GFX7, GFX8, GFX9", "gfx7-gfx8-gfx9-insts"),
FeatureInfo(@This()).create(.Gfx8Insts, "gfx8-insts", "Additional instructions for GFX8+", "gfx8-insts"),
FeatureInfo(@This()).createWithSubfeatures(.Gfx9, "gfx9", "GFX9 GPU generation", "gfx9", &[_]@This() {
.Gfx9Insts,
.Wavefrontsize64,
.Fp64,
.Gcn3Encoding,
.FastFmaf,
.Sdwa,
.SdwaScalar,
.VgprIndexMode,
.Dpp,
.AddNoCarryInsts,
.ApertureRegs,
.IntClampInsts,
.SdwaOmod,
.SdwaSdst,
.SdwaScalar,
.AddNoCarryInsts,
.ScalarAtomics,
.SMemrealtime,
.Gcn3Encoding,
.CiInsts,
.FlatAddressSpace,
.ScalarFlatScratchInsts,
.Gfx8Insts,
.Sdwa,
.Wavefrontsize64,
.SdwaSdst,
.FlatInstOffsets,
.ScalarStores,
.Gfx7Gfx8Gfx9Insts,
.R128A16,
.IntClampInsts,
.ScalarStores,
.ApertureRegs,
.CiInsts,
.FlatGlobalInsts,
.BitInsts16,
.FlatScratchInsts,
.SMemrealtime,
.Vop3p,
.FlatInstOffsets,
.Inv2piInlineImm,
.Dpp,
.Localmemorysize65536,
.Vop3p,
.BitInsts16,
.VgprIndexMode,
.Gfx8Insts,
.Inv2piInlineImm,
.Gfx9Insts,
.ScalarFlatScratchInsts,
.FlatGlobalInsts,
.FlatScratchInsts,
.Fp64,
.FastFmaf,
}),
FeatureInfo(@This()).create(.Gfx9Insts, "gfx9-insts", "Additional instructions for GFX9+", "gfx9-insts"),
FeatureInfo(@This()).createWithSubfeatures(.Gfx10, "gfx10", "GFX10 GPU generation", "gfx10", &[_]@This() {
.Gfx9Insts,
.Vscnt,
.ApertureRegs,
.Gfx10Insts,
.IntClampInsts,
.PkFmacF16Inst,
.SdwaOmod,
.SdwaScalar,
.AddNoCarryInsts,
.Movrel,
.SMemrealtime,
.NoSdstCmpx,
.CiInsts,
.FlatAddressSpace,
.Sdwa,
.NoSramEccSupport,
.SdwaSdst,
.FlatInstOffsets,
.RegisterBanking,
.Dpp,
.Localmemorysize65536,
.Vop3p,
.BitInsts16,
.Dpp8,
.Gfx8Insts,
.Inv2piInlineImm,
.Gfx9Insts,
.FmaMixInsts,
.MimgR128,
.Vop3Literal,
.FlatGlobalInsts,
.FlatScratchInsts,
.Fp64,
.FastFmaf,
.Sdwa,
.SdwaScalar,
.Dpp,
.RegisterBanking,
.Gfx10Insts,
.AddNoCarryInsts,
.SdwaOmod,
.SdwaSdst,
.FlatAddressSpace,
.Gfx8Insts,
.FmaMixInsts,
.PkFmacF16Inst,
.Vop3Literal,
.MimgR128,
.NoSramEccSupport,
.IntClampInsts,
.Movrel,
.Dpp8,
.ApertureRegs,
.NoDataDepHazard,
.CiInsts,
.FlatGlobalInsts,
.BitInsts16,
.FlatScratchInsts,
.SMemrealtime,
.Vop3p,
.FlatInstOffsets,
.Inv2piInlineImm,
.Localmemorysize65536,
.Vscnt,
}),
FeatureInfo(@This()).create(.Gfx10Insts, "gfx10-insts", "Additional instructions for GFX10+", "gfx10-insts"),
FeatureInfo(@This()).create(.InstFwdPrefetchBug, "inst-fwd-prefetch-bug", "S_INST_PREFETCH instruction causes shader to hang", "inst-fwd-prefetch-bug"),
@ -276,25 +276,25 @@ pub const AmdGpuFeature = enum {
FeatureInfo(@This()).create(.ScalarFlatScratchInsts, "scalar-flat-scratch-insts", "Have s_scratch_* flat memory instructions", "scalar-flat-scratch-insts"),
FeatureInfo(@This()).create(.ScalarStores, "scalar-stores", "Has store scalar memory instructions", "scalar-stores"),
FeatureInfo(@This()).createWithSubfeatures(.SeaIslands, "sea-islands", "SEA_ISLANDS GPU generation", "sea-islands", &[_]@This() {
.Wavefrontsize64,
.MimgR128,
.Movrel,
.Gfx7Gfx8Gfx9Insts,
.Fp64,
.TrigReducedRange,
.CiInsts,
.FlatAddressSpace,
.TrigReducedRange,
.NoSramEccSupport,
.Movrel,
.Localmemorysize65536,
.Gfx7Gfx8Gfx9Insts,
.Wavefrontsize64,
.NoSramEccSupport,
.MimgR128,
}),
FeatureInfo(@This()).createWithSubfeatures(.SouthernIslands, "southern-islands", "SOUTHERN_ISLANDS GPU generation", "southern-islands", &[_]@This() {
.Wavefrontsize64,
.Movrel,
.MimgR128,
.Fp64,
.NoXnackSupport,
.TrigReducedRange,
.NoXnackSupport,
.Wavefrontsize64,
.NoSramEccSupport,
.Movrel,
.Ldsbankcount32,
.Localmemorysize32768,
}),
@ -310,28 +310,28 @@ pub const AmdGpuFeature = enum {
FeatureInfo(@This()).create(.VcmpxExecWarHazard, "vcmpx-exec-war-hazard", "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)", "vcmpx-exec-war-hazard"),
FeatureInfo(@This()).create(.VcmpxPermlaneHazard, "vcmpx-permlane-hazard", "TODO: describe me", "vcmpx-permlane-hazard"),
FeatureInfo(@This()).createWithSubfeatures(.VolcanicIslands, "volcanic-islands", "VOLCANIC_ISLANDS GPU generation", "volcanic-islands", &[_]@This() {
.Wavefrontsize64,
.Fp64,
.IntClampInsts,
.SdwaMav,
.Movrel,
.SMemrealtime,
.Gcn3Encoding,
.TrigReducedRange,
.Sdwa,
.VgprIndexMode,
.Dpp,
.FlatAddressSpace,
.Gfx8Insts,
.Gfx7Gfx8Gfx9Insts,
.MimgR128,
.NoSramEccSupport,
.IntClampInsts,
.ScalarStores,
.Movrel,
.SdwaMav,
.CiInsts,
.BitInsts16,
.SMemrealtime,
.Inv2piInlineImm,
.FlatAddressSpace,
.Sdwa,
.Wavefrontsize64,
.NoSramEccSupport,
.ScalarStores,
.Gfx7Gfx8Gfx9Insts,
.Dpp,
.Localmemorysize65536,
.BitInsts16,
.VgprIndexMode,
.Gfx8Insts,
.Inv2piInlineImm,
.MimgR128,
.SdwaOutModsVopc,
.Fp64,
}),
FeatureInfo(@This()).create(.Vscnt, "vscnt", "Has separate store vscnt counter", "vscnt"),
FeatureInfo(@This()).create(.Wavefrontsize16, "wavefrontsize16", "The number of threads per wavefront", "wavefrontsize16"),

440
lib/std/target/feature/ArmFeature.zig
View File

@ -177,7 +177,7 @@ pub const ArmFeature = enum {
Swift,
Xscale,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
@ -215,283 +215,283 @@ pub const ArmFeature = enum {
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6M, "armv6-m", "ARMv6m architecture", "armv6-m", &[_]@This() {
.Mclass,
.StrictAlign,
.V4t,
.ThumbMode,
.Db,
.V4t,
.StrictAlign,
.Mclass,
.Noarm,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6sM, "armv6s-m", "ARMv6sm architecture", "armv6s-m", &[_]@This() {
.Mclass,
.StrictAlign,
.V4t,
.ThumbMode,
.Db,
.V4t,
.StrictAlign,
.Mclass,
.Noarm,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv6t2, "armv6t2", "ARMv6t2 architecture", "armv6t2", &[_]@This() {
.Thumb2,
.V4t,
.Thumb2,
.Dsp,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7A, "armv7-a", "ARMv7a architecture", "armv7-a", &[_]@This() {
.Thumb2,
.Perfmon,
.Db,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7eM, "armv7e-m", "ARMv7em architecture", "armv7e-m", &[_]@This() {
.Thumb2,
.Mclass,
.Perfmon,
.ThumbMode,
.Db,
.Dsp,
.V7clrex,
.V4t,
.Hwdiv,
.ThumbMode,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Mclass,
.Noarm,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7k, "armv7k", "ARMv7a architecture", "armv7k", &[_]@This() {
.Thumb2,
.Perfmon,
.Db,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7M, "armv7-m", "ARMv7m architecture", "armv7-m", &[_]@This() {
.Thumb2,
.Mclass,
.Perfmon,
.ThumbMode,
.Db,
.V7clrex,
.V4t,
.Hwdiv,
.ThumbMode,
.V7clrex,
.Thumb2,
.Db,
.Mclass,
.Noarm,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7R, "armv7-r", "ARMv7r architecture", "armv7-r", &[_]@This() {
.Thumb2,
.Perfmon,
.Db,
.Dsp,
.Rclass,
.V7clrex,
.V4t,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Hwdiv,
.Rclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7s, "armv7s", "ARMv7a architecture", "armv7s", &[_]@This() {
.Thumb2,
.Perfmon,
.Db,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv7ve, "armv7ve", "ARMv7ve architecture", "armv7ve", &[_]@This() {
.Thumb2,
.Mp,
.Perfmon,
.Db,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.Perfmon,
.D32,
.Mp,
.Fpregs,
.V4t,
.V7clrex,
.Dsp,
.Thumb2,
.Db,
.Aclass,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8A, "armv8-a", "ARMv8a architecture", "armv8-a", &[_]@This() {
.Thumb2,
.Mp,
.HwdivArm,
.Perfmon,
.Db,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.V7clrex,
.Db,
.Aclass,
.Trustzone,
.Thumb2,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8Mbase, "armv8-m.base", "ARMv8mBaseline architecture", "armv8-m.base", &[_]@This() {
.Mclass,
.StrictAlign,
.V4t,
.ThumbMode,
.Db,
.Msecext8,
.V7clrex,
.V4t,
.Hwdiv,
.Db,
.StrictAlign,
.Mclass,
.Noarm,
.AcquireRelease,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8Mmain, "armv8-m.main", "ARMv8mMainline architecture", "armv8-m.main", &[_]@This() {
.Thumb2,
.Mclass,
.Perfmon,
.V4t,
.ThumbMode,
.Db,
.Msecext8,
.V7clrex,
.V4t,
.Hwdiv,
.Thumb2,
.Db,
.Mclass,
.Noarm,
.AcquireRelease,
.Hwdiv,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv8R, "armv8-r", "ARMv8r architecture", "armv8-r", &[_]@This() {
.Thumb2,
.Mp,
.HwdivArm,
.Perfmon,
.Db,
.D32,
.Crc,
.Fp16,
.Fpregs,
.Mp,
.Dfb,
.Dsp,
.Rclass,
.V7clrex,
.Fp16,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.Db,
.V7clrex,
.Thumb2,
.AcquireRelease,
.Hwdiv,
.Rclass,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv81A, "armv8.1-a", "ARMv81a architecture", "armv8.1-a", &[_]@This() {
.Thumb2,
.Mp,
.HwdivArm,
.Perfmon,
.Db,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.V7clrex,
.Db,
.Aclass,
.Trustzone,
.Thumb2,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv81Mmain, "armv8.1-m.main", "ARMv81mMainline architecture", "armv8.1-m.main", &[_]@This() {
.Thumb2,
.Mclass,
.Perfmon,
.ThumbMode,
.Db,
.Msecext8,
.Ras,
.V7clrex,
.V4t,
.Hwdiv,
.ThumbMode,
.Msecext8,
.V7clrex,
.Thumb2,
.Db,
.Ras,
.Mclass,
.Noarm,
.Lob,
.AcquireRelease,
.Hwdiv,
.Lob,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv82A, "armv8.2-a", "ARMv82a architecture", "armv8.2-a", &[_]@This() {
.Thumb2,
.Mp,
.Perfmon,
.Db,
.Crc,
.Fp16,
.Ras,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Trustzone,
.Thumb2,
.Ras,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv83A, "armv8.3-a", "ARMv83a architecture", "armv8.3-a", &[_]@This() {
.Thumb2,
.Mp,
.Perfmon,
.Db,
.Crc,
.Fp16,
.Ras,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Trustzone,
.Thumb2,
.Ras,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv84A, "armv8.4-a", "ARMv84a architecture", "armv8.4-a", &[_]@This() {
.Thumb2,
.Mp,
.Perfmon,
.Db,
.Crc,
.Fp16,
.Ras,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Trustzone,
.Thumb2,
.Ras,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).createWithSubfeatures(.Armv85A, "armv8.5-a", "ARMv85a architecture", "armv8.5-a", &[_]@This() {
.Thumb2,
.Mp,
.Perfmon,
.Sb,
.Db,
.Crc,
.Fp16,
.Ras,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Hwdiv,
.HwdivArm,
.Perfmon,
.D32,
.Fpregs,
.Crc,
.Mp,
.Fp16,
.Dsp,
.V4t,
.V7clrex,
.Db,
.Aclass,
.Trustzone,
.Thumb2,
.Ras,
.Sb,
.AcquireRelease,
.Hwdiv,
.Trustzone,
}),
FeatureInfo(@This()).create(.Msecext8, "8msecext", "Enable support for ARMv8-M Security Extensions", "8msecext"),
FeatureInfo(@This()).create(.Aclass, "aclass", "Is application profile ('A' series)", "aclass"),
FeatureInfo(@This()).createWithSubfeatures(.Aes, "aes", "Enable AES support", "aes", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.AcquireRelease, "acquire-release", "Has v8 acquire/release (lda/ldaex etc) instructions", "acquire-release"),
FeatureInfo(@This()).create(.AvoidMovsShop, "avoid-movs-shop", "Avoid movs instructions with shifter operand", "avoid-movs-shop"),
@ -500,8 +500,8 @@ pub const ArmFeature = enum {
FeatureInfo(@This()).create(.CheapPredicableCpsr, "cheap-predicable-cpsr", "Disable +1 predication cost for instructions updating CPSR", "cheap-predicable-cpsr"),
FeatureInfo(@This()).create(.VldnAlign, "vldn-align", "Check for VLDn unaligned access", "vldn-align"),
FeatureInfo(@This()).createWithSubfeatures(.Crypto, "crypto", "Enable support for Cryptography extensions", "crypto", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.D32, "d32", "Extend FP to 32 double registers", "d32"),
FeatureInfo(@This()).create(.Db, "db", "Has data barrier (dmb/dsb) instructions", "db"),
@ -509,37 +509,37 @@ pub const ArmFeature = enum {
FeatureInfo(@This()).create(.Dsp, "dsp", "Supports DSP instructions in ARM and/or Thumb2", "dsp"),
FeatureInfo(@This()).create(.DontWidenVmovs, "dont-widen-vmovs", "Don't widen VMOVS to VMOVD", "dont-widen-vmovs"),
FeatureInfo(@This()).createWithSubfeatures(.Dotprod, "dotprod", "Enable support for dot product instructions", "dotprod", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.ExecuteOnly, "execute-only", "Enable the generation of execute only code.", "execute-only"),
FeatureInfo(@This()).create(.ExpandFpMlx, "expand-fp-mlx", "Expand VFP/NEON MLA/MLS instructions", "expand-fp-mlx"),
FeatureInfo(@This()).create(.Fp16, "fp16", "Enable half-precision floating point", "fp16"),
FeatureInfo(@This()).createWithSubfeatures(.Fp16fml, "fp16fml", "Enable full half-precision floating point fml instructions", "fp16fml", &[_]@This() {
.Fp16,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fp64, "fp64", "Floating point unit supports double precision", "fp64", &[_]@This() {
.Fpregs,
}),
FeatureInfo(@This()).create(.Fpao, "fpao", "Enable fast computation of positive address offsets", "fpao"),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8, "fp-armv8", "Enable ARMv8 FP", "fp-armv8", &[_]@This() {
.Fp16,
.Fpregs,
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16, "fp-armv8d16", "Enable ARMv8 FP with only 16 d-registers", "fp-armv8d16", &[_]@This() {
.Fp16,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8d16sp, "fp-armv8d16sp", "Enable ARMv8 FP with only 16 d-registers and no double precision", "fp-armv8d16sp", &[_]@This() {
.Fp16,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.FpArmv8sp, "fp-armv8sp", "Enable ARMv8 FP with no double precision", "fp-armv8sp", &[_]@This() {
.Fp16,
.Fpregs,
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).create(.Fpregs, "fpregs", "Enable FP registers", "fpregs"),
FeatureInfo(@This()).createWithSubfeatures(.Fpregs16, "fpregs16", "Enable 16-bit FP registers", "fpregs16", &[_]@This() {
@ -549,8 +549,8 @@ pub const ArmFeature = enum {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Fullfp16, "fullfp16", "Enable full half-precision floating point", "fullfp16", &[_]@This() {
.Fp16,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).create(.FuseAes, "fuse-aes", "CPU fuses AES crypto operations", "fuse-aes"),
FeatureInfo(@This()).create(.FuseLiterals, "fuse-literals", "CPU fuses literal generation operations", "fuse-literals"),
@ -569,8 +569,8 @@ pub const ArmFeature = enum {
FeatureInfo(@This()).create(.Mve4beat, "mve4beat", "Model MVE instructions as a 4 beats per tick architecture", "mve4beat"),
FeatureInfo(@This()).create(.MuxedUnits, "muxed-units", "Has muxed AGU and NEON/FPU", "muxed-units"),
FeatureInfo(@This()).createWithSubfeatures(.Neon, "neon", "Enable NEON instructions", "neon", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.Neonfp, "neonfp", "Use NEON for single precision FP", "neonfp"),
FeatureInfo(@This()).create(.NeonFpmovs, "neon-fpmovs", "Convert VMOVSR, VMOVRS, VMOVS to NEON", "neon-fpmovs"),
@ -592,8 +592,8 @@ pub const ArmFeature = enum {
FeatureInfo(@This()).create(.ReserveR9, "reserve-r9", "Reserve R9, making it unavailable as GPR", "reserve-r9"),
FeatureInfo(@This()).create(.Sb, "sb", "Enable v8.5a Speculation Barrier", "sb"),
FeatureInfo(@This()).createWithSubfeatures(.Sha2, "sha2", "Enable SHA1 and SHA256 support", "sha2", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).create(.SlowFpBrcc, "slow-fp-brcc", "FP compare + branch is slow", "slow-fp-brcc"),
FeatureInfo(@This()).create(.SlowLoadDSubreg, "slow-load-D-subreg", "Loading into D subregs is slow", "slow-load-D-subreg"),
@ -617,8 +617,8 @@ pub const ArmFeature = enum {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3, "vfp3", "Enable VFP3 instructions", "vfp3", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3d16, "vfp3d16", "Enable VFP3 instructions with only 16 d-registers", "vfp3d16", &[_]@This() {
.Fpregs,
@ -627,26 +627,26 @@ pub const ArmFeature = enum {
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp3sp, "vfp3sp", "Enable VFP3 instructions with no double precision", "vfp3sp", &[_]@This() {
.Fpregs,
.D32,
.Fpregs,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4, "vfp4", "Enable VFP4 instructions", "vfp4", &[_]@This() {
.Fp16,
.Fpregs,
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16, "vfp4d16", "Enable VFP4 instructions with only 16 d-registers", "vfp4d16", &[_]@This() {
.Fp16,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4d16sp, "vfp4d16sp", "Enable VFP4 instructions with only 16 d-registers and no double precision", "vfp4d16sp", &[_]@This() {
.Fp16,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).createWithSubfeatures(.Vfp4sp, "vfp4sp", "Enable VFP4 instructions with no double precision", "vfp4sp", &[_]@This() {
.Fp16,
.Fpregs,
.D32,
.Fpregs,
.Fp16,
}),
FeatureInfo(@This()).create(.VmlxForwarding, "vmlx-forwarding", "Has multiplier accumulator forwarding", "vmlx-forwarding"),
FeatureInfo(@This()).createWithSubfeatures(.Virtualization, "virtualization", "Supports Virtualization extension", "virtualization", &[_]@This() {
@ -655,21 +655,21 @@ pub const ArmFeature = enum {
}),
FeatureInfo(@This()).create(.Zcz, "zcz", "Has zero-cycle zeroing instructions", "zcz"),
FeatureInfo(@This()).createWithSubfeatures(.Mvefp, "mve.fp", "Support M-Class Vector Extension with integer and floating ops", "mve.fp", &[_]@This() {
.Thumb2,
.Perfmon,
.V4t,
.Fpregs,
.V7clrex,
.Fp16,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.Thumb2,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mve, "mve", "Support M-Class Vector Extension with integer ops", "mve", &[_]@This() {
.Thumb2,
.Perfmon,
.Dsp,
.V7clrex,
.V4t,
.Fpregs,
.V7clrex,
.Dsp,
.Thumb2,
}),
FeatureInfo(@This()).create(.V4t, "v4t", "Support ARM v4T instructions", "v4t"),
FeatureInfo(@This()).createWithSubfeatures(.V5te, "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", "v5te", &[_]@This() {
@ -688,76 +688,76 @@ pub const ArmFeature = enum {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V6t2, "v6t2", "Support ARM v6t2 instructions", "v6t2", &[_]@This() {
.Thumb2,
.V4t,
.Thumb2,
}),
FeatureInfo(@This()).createWithSubfeatures(.V7, "v7", "Support ARM v7 instructions", "v7", &[_]@This() {
.V7clrex,
.V4t,
.Perfmon,
.Thumb2,
.V4t,
.V7clrex,
}),
FeatureInfo(@This()).createWithSubfeatures(.V8m, "v8m", "Support ARM v8M Baseline instructions", "v8m", &[_]@This() {
.V4t,
}),
FeatureInfo(@This()).createWithSubfeatures(.V8mmain, "v8m.main", "Support ARM v8M Mainline instructions", "v8m.main", &[_]@This() {
.V7clrex,
.V4t,
.Perfmon,
.Thumb2,
.V4t,
.V7clrex,
}),
FeatureInfo(@This()).createWithSubfeatures(.V8, "v8", "Support ARM v8 instructions", "v8", &[_]@This() {
.Thumb2,
.Perfmon,
.V7clrex,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V81mmain, "v8.1m.main", "Support ARM v8-1M Mainline instructions", "v8.1m.main", &[_]@This() {
.V7clrex,
.V4t,
.Perfmon,
.Thumb2,
.V4t,
.V7clrex,
}),
FeatureInfo(@This()).createWithSubfeatures(.V81a, "v8.1a", "Support ARM v8.1a instructions", "v8.1a", &[_]@This() {
.Thumb2,
.Perfmon,
.V7clrex,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V82a, "v8.2a", "Support ARM v8.2a instructions", "v8.2a", &[_]@This() {
.Thumb2,
.Perfmon,
.V7clrex,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V83a, "v8.3a", "Support ARM v8.3a instructions", "v8.3a", &[_]@This() {
.Thumb2,
.Perfmon,
.V7clrex,
.V4t,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V84a, "v8.4a", "Support ARM v8.4a instructions", "v8.4a", &[_]@This() {
.Thumb2,
.Perfmon,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Fpregs,
.V7clrex,
.Thumb2,
.AcquireRelease,
}),
FeatureInfo(@This()).createWithSubfeatures(.V85a, "v8.5a", "Support ARM v8.5a instructions", "v8.5a", &[_]@This() {
.Thumb2,
.Perfmon,
.Sb,
.V7clrex,
.V4t,
.Fpregs,
.D32,
.Fpregs,
.V7clrex,
.Thumb2,
.AcquireRelease,
.Sb,
}),
FeatureInfo(@This()).createWithSubfeatures(.Iwmmxt, "iwmmxt", "ARMv5te architecture", "iwmmxt", &[_]@This() {
.V4t,
@ -784,24 +784,24 @@ pub const ArmFeature = enum {
FeatureInfo(@This()).create(.A75, "a75", "Cortex-A75 ARM processors", "a75"),
FeatureInfo(@This()).create(.A76, "a76", "Cortex-A76 ARM processors", "a76"),
FeatureInfo(@This()).createWithSubfeatures(.Exynos, "exynos", "Samsung Exynos processors", "exynos", &[_]@This() {
.Zcz,
.SlowVdup32,
.SlowVgetlni32,
.DontWidenVmovs,
.Crc,
.FuseAes,
.WideStrideVfp,
.ProfUnpr,
.Slowfpvmlx,
.SlowFpBrcc,
.FuseLiterals,
.Fpregs,
.D32,
.ExpandFpMlx,
.Hwdiv,
.HwdivArm,
.D32,
.Crc,
.Fpregs,
.RetAddrStack,
.SlowVgetlni32,
.WideStrideVfp,
.SlowVdup32,
.SlowFpBrcc,
.ProfUnpr,
.DontWidenVmovs,
.Zcz,
.Hwdiv,
.FuseAes,
.Slowfpvmlx,
.UseAa,
.FuseLiterals,
.ExpandFpMlx,
}),
FeatureInfo(@This()).create(.Krait, "krait", "Qualcomm Krait processors", "krait"),
FeatureInfo(@This()).create(.Kryo, "kryo", "Qualcomm Kryo processors", "kryo"),

196
lib/std/target/feature/AvrFeature.zig
View File

@ -35,160 +35,160 @@ pub const AvrFeature = enum {
Smallstack,
Tinyencoding,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
pub const feature_infos = [@memberCount(@This())]FeatureInfo(@This()) {
FeatureInfo(@This()).create(.Avr0, "avr0", "The device is a part of the avr0 family", "avr0"),
FeatureInfo(@This()).createWithSubfeatures(.Avr1, "avr1", "The device is a part of the avr1 family", "avr1", &[_]@This() {
.Lpm,
.Avr0,
.Lpm,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr2, "avr2", "The device is a part of the avr2 family", "avr2", &[_]@This() {
.Ijmpcall,
.Sram,
.Avr0,
.Addsubiw,
.Lpm,
.Avr0,
.Sram,
.Addsubiw,
.Ijmpcall,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr3, "avr3", "The device is a part of the avr3 family", "avr3", &[_]@This() {
.Ijmpcall,
.Sram,
.Lpm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpm,
.Ijmpcall,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr4, "avr4", "The device is a part of the avr4 family", "avr4", &[_]@This() {
.Ijmpcall,
.Movw,
.Mul,
.Sram,
.Break,
.Spm,
.Lpmx,
.Avr0,
.Addsubiw,
.Lpm,
.Movw,
.Spm,
.Avr0,
.Sram,
.Addsubiw,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr5, "avr5", "The device is a part of the avr5 family", "avr5", &[_]@This() {
.Ijmpcall,
.Lpm,
.Movw,
.Mul,
.Sram,
.Break,
.Spm,
.Lpmx,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpm,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr6, "avr6", "The device is a part of the avr6 family", "avr6", &[_]@This() {
.Ijmpcall,
.Elpmx,
.Movw,
.Mul,
.Sram,
.Break,
.Spm,
.Lpm,
.Elpm,
.Lpmx,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpm,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr25, "avr25", "The device is a part of the avr25 family", "avr25", &[_]@This() {
.Ijmpcall,
.Movw,
.Sram,
.Break,
.Spm,
.Lpmx,
.Avr0,
.Addsubiw,
.Lpm,
.Movw,
.Spm,
.Avr0,
.Sram,
.Addsubiw,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr31, "avr31", "The device is a part of the avr31 family", "avr31", &[_]@This() {
.Ijmpcall,
.Sram,
.Lpm,
.Elpm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpm,
.Ijmpcall,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr35, "avr35", "The device is a part of the avr35 family", "avr35", &[_]@This() {
.Ijmpcall,
.Lpm,
.Movw,
.Sram,
.Break,
.Spm,
.Lpmx,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpm,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avr51, "avr51", "The device is a part of the avr51 family", "avr51", &[_]@This() {
.Ijmpcall,
.Elpmx,
.Movw,
.Mul,
.Sram,
.Break,
.Spm,
.Lpm,
.Elpm,
.Lpmx,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Addsubiw,
.Lpm,
.Mul,
.Lpmx,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Avrtiny, "avrtiny", "The device is a part of the avrtiny family", "avrtiny", &[_]@This() {
.Avr0,
.Sram,
.Break,
.Tinyencoding,
.Avr0,
.Sram,
}),
FeatureInfo(@This()).createWithSubfeatures(.Xmega, "xmega", "The device is a part of the xmega family", "xmega", &[_]@This() {
.Ijmpcall,
.Elpmx,
.Movw,
.Eijmpcall,
.Mul,
.Sram,
.Break,
.Spm,
.Elpm,
.Lpmx,
.Spmx,
.Avr0,
.Jmpcall,
.Addsubiw,
.Lpm,
.Elpm,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Eijmpcall,
.Spmx,
.Addsubiw,
.Mul,
.Lpmx,
.Des,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).createWithSubfeatures(.Xmegau, "xmegau", "The device is a part of the xmegau family", "xmegau", &[_]@This() {
.Ijmpcall,
.Elpmx,
.Movw,
.Eijmpcall,
.Mul,
.Rmw,
.Sram,
.Break,
.Spm,
.Elpm,
.Lpmx,
.Spmx,
.Avr0,
.Jmpcall,
.Addsubiw,
.Lpm,
.Elpm,
.Movw,
.Elpmx,
.Spm,
.Avr0,
.Sram,
.Jmpcall,
.Eijmpcall,
.Spmx,
.Addsubiw,
.Mul,
.Lpmx,
.Rmw,
.Des,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).create(.Addsubiw, "addsubiw", "Enable 16-bit register-immediate addition and subtraction instructions", "addsubiw"),
FeatureInfo(@This()).create(.Break, "break", "The device supports the `BREAK` debugging instruction", "break"),
@ -207,22 +207,22 @@ pub const AvrFeature = enum {
FeatureInfo(@This()).create(.Spmx, "spmx", "The device supports the `SPM Z+` instruction", "spmx"),
FeatureInfo(@This()).create(.Sram, "sram", "The device has random access memory", "sram"),
FeatureInfo(@This()).createWithSubfeatures(.Special, "special", "Enable use of the entire instruction set - used for debugging", "special", &[_]@This() {
.Ijmpcall,
.Lpm,
.Elpm,
.Elpmx,
.Movw,
.Eijmpcall,
.Mul,
.Rmw,
.Sram,
.Break,
.Elpm,
.Spm,
.Lpmx,
.Eijmpcall,
.Spmx,
.Jmpcall,
.Sram,
.Addsubiw,
.Lpm,
.Mul,
.Lpmx,
.Rmw,
.Des,
.Ijmpcall,
.Break,
}),
FeatureInfo(@This()).create(.Smallstack, "smallstack", "The device has an 8-bit stack pointer", "smallstack"),
FeatureInfo(@This()).create(.Tinyencoding, "tinyencoding", "The device has Tiny core specific instruction encodings", "tinyencoding"),

2
lib/std/target/feature/BpfFeature.zig
View File

@ -5,7 +5,7 @@ pub const BpfFeature = enum {
Dummy,
Dwarfris,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/HexagonFeature.zig
View File

@ -26,7 +26,7 @@ pub const HexagonFeature = enum {
ReservedR19,
SmallData,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

166
lib/std/target/feature/MipsFeature.zig
View File

@ -52,7 +52,7 @@ pub const MipsFeature = enum {
Xgot,
P5600,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
@ -60,14 +60,14 @@ pub const MipsFeature = enum {
FeatureInfo(@This()).create(.Abs2008, "abs2008", "Disable IEEE 754-2008 abs.fmt mode", "abs2008"),
FeatureInfo(@This()).create(.Crc, "crc", "Mips R6 CRC ASE", "crc"),
FeatureInfo(@This()).createWithSubfeatures(.Cnmips, "cnmips", "Octeon cnMIPS Support", "cnmips", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Dsp, "dsp", "Mips DSP ASE", "dsp"),
FeatureInfo(@This()).createWithSubfeatures(.Dspr2, "dspr2", "Mips DSP-R2 ASE", "dspr2", &[_]@This() {
@ -91,128 +91,128 @@ pub const MipsFeature = enum {
.Mips1,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips3, "mips3", "MIPS III ISA Support [highly experimental]", "mips3", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips3_32r2,
.Mips1,
.Fp64,
.Gp64,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Mips3_32, "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", "mips3_32"),
FeatureInfo(@This()).create(.Mips3_32r2, "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", "mips3_32r2"),
FeatureInfo(@This()).createWithSubfeatures(.Mips4, "mips4", "MIPS IV ISA Support", "mips4", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Mips4_32, "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", "mips4_32"),
FeatureInfo(@This()).create(.Mips4_32r2, "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", "mips4_32r2"),
FeatureInfo(@This()).createWithSubfeatures(.Mips5, "mips5", "MIPS V ISA Support [highly experimental]", "mips5", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Mips5_32r2, "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", "mips5_32r2"),
FeatureInfo(@This()).create(.Mips16, "mips16", "Mips16 mode", "mips16"),
FeatureInfo(@This()).createWithSubfeatures(.Mips32, "mips32", "Mips32 ISA Support", "mips32", &[_]@This() {
.Mips3_32,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r2, "mips32r2", "Mips32r2 ISA Support", "mips32r2", &[_]@This() {
.Mips3_32,
.Mips5_32r2,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips5_32r2,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r3, "mips32r3", "Mips32r3 ISA Support", "mips32r3", &[_]@This() {
.Mips3_32,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r5, "mips32r5", "Mips32r5 ISA Support", "mips32r5", &[_]@This() {
.Mips3_32,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips32r6, "mips32r6", "Mips32r6 ISA Support [experimental]", "mips32r6", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Abs2008,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Nan2008,
.Mips5_32r2,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64, "mips64", "Mips64 ISA Support", "mips64", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r2, "mips64r2", "Mips64r2 ISA Support", "mips64r2", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r3, "mips64r3", "Mips64r3 ISA Support", "mips64r3", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r5, "mips64r5", "Mips64r5 ISA Support", "mips64r5", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Gp64,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Gp64,
.Fp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).createWithSubfeatures(.Mips64r6, "mips64r6", "Mips64r6 ISA Support [experimental]", "mips64r6", &[_]@This() {
.Mips3_32,
.Fp64,
.Mips4_32r2,
.Abs2008,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Nan2008,
.Gp64,
.Mips5_32r2,
.Mips3_32r2,
.Nan2008,
.Abs2008,
.Mips4_32r2,
.Fp64,
.Gp64,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
FeatureInfo(@This()).create(.Nan2008, "nan2008", "IEEE 754-2008 NaN encoding", "nan2008"),
FeatureInfo(@This()).create(.Noabicalls, "noabicalls", "Disable SVR4-style position-independent code", "noabicalls"),
@ -227,12 +227,12 @@ pub const MipsFeature = enum {
FeatureInfo(@This()).create(.Virt, "virt", "Mips Virtualization ASE", "virt"),
FeatureInfo(@This()).create(.Xgot, "xgot", "Assume 32-bit GOT", "xgot"),
FeatureInfo(@This()).createWithSubfeatures(.P5600, "p5600", "The P5600 Processor", "p5600", &[_]@This() {
.Mips3_32,
.Mips4_32r2,
.Mips3_32r2,
.Mips1,
.Mips4_32,
.Mips5_32r2,
.Mips3_32r2,
.Mips4_32r2,
.Mips4_32,
.Mips1,
.Mips3_32,
}),
};
};

2
lib/std/target/feature/Msp430Feature.zig
View File

@ -6,7 +6,7 @@ pub const Msp430Feature = enum {
Hwmultf5,
Ext,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/NvptxFeature.zig
View File

@ -27,7 +27,7 @@ pub const NvptxFeature = enum {
Sm_72,
Sm_75,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/PowerPcFeature.zig
View File

@ -53,7 +53,7 @@ pub const PowerPcFeature = enum {
Vsx,
VectorsUseTwoUnits,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/RiscVFeature.zig
View File

@ -11,7 +11,7 @@ pub const RiscVFeature = enum {
F,
M,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/SparcFeature.zig
View File

@ -21,7 +21,7 @@ pub const SparcFeature = enum {
Hasumacsmac,
Popc,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/SystemZFeature.zig
View File

@ -37,7 +37,7 @@ pub const SystemZFeature = enum {
VectorPackedDecimal,
VectorPackedDecimalEnhancement,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

2
lib/std/target/feature/WebAssemblyFeature.zig
View File

@ -12,7 +12,7 @@ pub const WebAssemblyFeature = enum {
TailCall,
UnimplementedSimd128,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}

4
lib/std/target/feature/X86Feature.zig
View File

@ -128,7 +128,7 @@ pub const X86Feature = enum {
BitMode32,
BitMode64,
pub fn getInfo(self: @This()) FeatureInfo {
pub fn getInfo(self: @This()) FeatureInfo(@This()) {
return feature_infos[@enumToInt(self)];
}
@ -254,8 +254,8 @@ pub const X86Feature = enum {
FeatureInfo(@This()).create(.Rdseed, "rdseed", "Support RDSEED instruction", "rdseed"),
FeatureInfo(@This()).create(.Rtm, "rtm", "Support RTM instructions", "rtm"),
FeatureInfo(@This()).createWithSubfeatures(.Retpoline, "retpoline", "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", "retpoline", &[_]@This() {
.RetpolineIndirectBranches,
.RetpolineIndirectCalls,
.RetpolineIndirectBranches,
}),
FeatureInfo(@This()).createWithSubfeatures(.RetpolineExternalThunk, "retpoline-external-thunk", "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", "retpoline-external-thunk", &[_]@This() {
.RetpolineIndirectCalls,

4
lib/std/target/feature/empty.zig
View File

@ -1,5 +1,5 @@
const FeatureInfo = @import("std").target.feature.FeatureInfo;
pub const EmptyFeature = enum {
pub const EmptyFeature = struct {
pub const feature_infos = [0]FeatureInfo(@This()) {};
}
};