54 lines
2.0 KiB
Zig
54 lines
2.0 KiB
Zig
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// zig fmt: off
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pub const Register = enum(u8) {
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// 0 through 15, 64-bit registers. 8-15 are extended.
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// id is just the int value.
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rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi,
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r8, r9, r10, r11, r12, r13, r14, r15,
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// 16 through 31, 32-bit registers. 24-31 are extended.
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// id is int value - 16.
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eax, ecx, edx, ebx, esp, ebp, esi, edi,
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r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d,
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// 32-47, 16-bit registers. 40-47 are extended.
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// id is int value - 32.
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ax, cx, dx, bx, sp, bp, si, di,
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r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w,
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// 48-63, 8-bit registers. 56-63 are extended.
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// id is int value - 48.
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al, bl, cl, dl, ah, ch, dh, bh,
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r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b,
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/// Returns the bit-width of the register.
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pub fn size(self: @This()) u7 {
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return switch (@enumToInt(self)) {
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0...15 => 64,
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16...31 => 32,
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32...47 => 16,
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48...64 => 8,
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else => unreachable,
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};
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}
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/// Returns whether the register is *extended*. Extended registers are the
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/// new registers added with amd64, r8 through r15. This also includes any
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/// other variant of access to those registers, such as r8b, r15d, and so
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/// on. This is needed because access to these registers requires special
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/// handling via the REX prefix, via the B or R bits, depending on context.
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pub fn isExtended(self: @This()) bool {
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return @enumToInt(self) & 0x08 != 0;
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}
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/// This returns the 4-bit register ID, which is used in practically every
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/// opcode. Note that bit 3 (the highest bit) is *never* used directly in
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/// an instruction (@see isExtended), and requires special handling. The
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/// lower three bits are often embedded directly in instructions (such as
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/// the B8 variant of moves), or used in R/M bytes.
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pub fn id(self: @This()) u4 {
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return @truncate(u4, @enumToInt(self));
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}
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};
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// zig fmt: on
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