2019-03-07 09:16:10 -08:00
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/* Defines for bits in AT_HWCAP and AT_HWCAP2.
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2020-03-03 19:46:57 -08:00
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Copyright (C) 2012-2020 Free Software Foundation, Inc.
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2019-03-07 09:16:10 -08:00
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with the GNU C Library; if not, see
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2020-03-03 19:46:57 -08:00
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<https://www.gnu.org/licenses/>. */
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2019-03-07 09:16:10 -08:00
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#if !defined(_SYS_AUXV_H) && !defined(_SYSDEPS_SYSDEP_H)
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# error "Never include <bits/hwcap.h> directly; use <sys/auxv.h> instead."
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#endif
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/* The bit numbers must match those in the kernel's asm/cputable.h. */
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/* Feature definitions in AT_HWCAP. */
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#define PPC_FEATURE_32 0x80000000 /* 32-bit mode. */
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#define PPC_FEATURE_64 0x40000000 /* 64-bit mode. */
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#define PPC_FEATURE_601_INSTR 0x20000000 /* 601 chip, Old POWER ISA. */
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#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 /* SIMD/Vector Unit. */
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#define PPC_FEATURE_HAS_FPU 0x08000000 /* Floating Point Unit. */
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#define PPC_FEATURE_HAS_MMU 0x04000000 /* Memory Management Unit. */
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#define PPC_FEATURE_HAS_4xxMAC 0x02000000 /* 4xx Multiply Accumulator. */
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#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 /* Unified I/D cache. */
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#define PPC_FEATURE_HAS_SPE 0x00800000 /* Signal Processing ext. */
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#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 /* SPE Float. */
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#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 /* SPE Double. */
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#define PPC_FEATURE_NO_TB 0x00100000 /* 601/403gx have no timebase */
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#define PPC_FEATURE_POWER4 0x00080000 /* POWER4 ISA 2.00 */
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#define PPC_FEATURE_POWER5 0x00040000 /* POWER5 ISA 2.02 */
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#define PPC_FEATURE_POWER5_PLUS 0x00020000 /* POWER5+ ISA 2.03 */
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#define PPC_FEATURE_CELL_BE 0x00010000 /* CELL Broadband Engine */
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#define PPC_FEATURE_BOOKE 0x00008000 /* ISA Category Embedded */
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#define PPC_FEATURE_SMT 0x00004000 /* Simultaneous
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Multi-Threading */
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#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
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#define PPC_FEATURE_ARCH_2_05 0x00001000 /* ISA 2.05 */
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#define PPC_FEATURE_PA6T 0x00000800 /* PA Semi 6T Core */
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#define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal FP Unit */
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#define PPC_FEATURE_POWER6_EXT 0x00000200 /* P6 + mffgpr/mftgpr */
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#define PPC_FEATURE_ARCH_2_06 0x00000100 /* ISA 2.06 */
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#define PPC_FEATURE_HAS_VSX 0x00000080 /* P7 Vector Extension. */
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#define PPC_FEATURE_PSERIES_PERFMON_COMPAT 0x00000040
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/* Reserved by the kernel. 0x00000004 Do not use. */
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#define PPC_FEATURE_TRUE_LE 0x00000002
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#define PPC_FEATURE_PPC_LE 0x00000001
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/* Feature definitions in AT_HWCAP2. */
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#define PPC_FEATURE2_ARCH_2_07 0x80000000 /* ISA 2.07 */
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#define PPC_FEATURE2_HAS_HTM 0x40000000 /* Hardware Transactional
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Memory */
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#define PPC_FEATURE2_HAS_DSCR 0x20000000 /* Data Stream Control
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Register */
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#define PPC_FEATURE2_HAS_EBB 0x10000000 /* Event Base Branching */
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#define PPC_FEATURE2_HAS_ISEL 0x08000000 /* Integer Select */
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#define PPC_FEATURE2_HAS_TAR 0x04000000 /* Target Address Register */
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#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000 /* Target supports vector
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instruction. */
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#define PPC_FEATURE2_HTM_NOSC 0x01000000 /* Kernel aborts transaction
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when a syscall is made. */
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#define PPC_FEATURE2_ARCH_3_00 0x00800000 /* ISA 3.0 */
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#define PPC_FEATURE2_HAS_IEEE128 0x00400000 /* VSX IEEE Binary Float
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128-bit */
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#define PPC_FEATURE2_DARN 0x00200000 /* darn instruction. */
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#define PPC_FEATURE2_SCV 0x00100000 /* scv syscall. */
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#define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM without suspended
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state. */
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