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zig/lib/std/target/riscv.zig

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import data from llvm 9
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const std = @import("../std.zig");
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
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const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
Switch CPU/features to simple format
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import data from llvm 9
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pub const Feature = enum {
@"64bit",
a,
c,
d,
e,
f,
m,
relax,
update target CPUs and features with llvm10's data based on zig-llvm-target-details-generator commit 3aef1b9b4415ed3acfaea4ce8bc233e213548f71
2020-01-30 08:31:41 -08:00
reserve_x1,
reserve_x10,
reserve_x11,
reserve_x12,
reserve_x13,
reserve_x14,
reserve_x15,
reserve_x16,
reserve_x17,
reserve_x18,
reserve_x19,
reserve_x2,
reserve_x20,
reserve_x21,
reserve_x22,
reserve_x23,
reserve_x24,
reserve_x25,
reserve_x26,
reserve_x27,
reserve_x28,
reserve_x29,
reserve_x3,
reserve_x30,
reserve_x31,
reserve_x4,
reserve_x5,
reserve_x6,
reserve_x7,
reserve_x8,
reserve_x9,
rvc_hints,
Switch CPU/features to simple format
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};
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
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pub usingnamespace CpuFeature.feature_set_fns(Feature);
Switch CPU/features to simple format
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import data from llvm 9
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pub const all_features = blk: {
const len = @typeInfo(Feature).Enum.fields.len;
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
import data from llvm 9
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result[@enumToInt(Feature.@"64bit")] = .{
.llvm_name = "64bit",
.description = "Implements RV64",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
result[@enumToInt(Feature.a)] = .{
.llvm_name = "a",
.description = "'A' (Atomic Instructions)",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
result[@enumToInt(Feature.c)] = .{
.llvm_name = "c",
.description = "'C' (Compressed Instructions)",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
result[@enumToInt(Feature.d)] = .{
.llvm_name = "d",
.description = "'D' (Double-Precision Floating-Point)",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{
import data from llvm 9
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.f,
}),
};
result[@enumToInt(Feature.e)] = .{
.llvm_name = "e",
.description = "Implements RV32E (provides 16 rather than 32 GPRs)",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
result[@enumToInt(Feature.f)] = .{
.llvm_name = "f",
.description = "'F' (Single-Precision Floating-Point)",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
result[@enumToInt(Feature.m)] = .{
.llvm_name = "m",
.description = "'M' (Integer Multiplication and Division)",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
result[@enumToInt(Feature.relax)] = .{
.llvm_name = "relax",
.description = "Enable Linker relaxation.",
lazily compute the full cpu features dependencies
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.dependencies = featureSet(&[_]Feature{}),
import data from llvm 9
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};
update target CPUs and features with llvm10's data based on zig-llvm-target-details-generator commit 3aef1b9b4415ed3acfaea4ce8bc233e213548f71
2020-01-30 08:31:41 -08:00
result[@enumToInt(Feature.reserve_x1)] = .{
.llvm_name = "reserve-x1",
.description = "Reserve X1",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x10)] = .{
.llvm_name = "reserve-x10",
.description = "Reserve X10",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x11)] = .{
.llvm_name = "reserve-x11",
.description = "Reserve X11",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x12)] = .{
.llvm_name = "reserve-x12",
.description = "Reserve X12",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x13)] = .{
.llvm_name = "reserve-x13",
.description = "Reserve X13",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x14)] = .{
.llvm_name = "reserve-x14",
.description = "Reserve X14",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x15)] = .{
.llvm_name = "reserve-x15",
.description = "Reserve X15",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x16)] = .{
.llvm_name = "reserve-x16",
.description = "Reserve X16",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x17)] = .{
.llvm_name = "reserve-x17",
.description = "Reserve X17",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x18)] = .{
.llvm_name = "reserve-x18",
.description = "Reserve X18",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x19)] = .{
.llvm_name = "reserve-x19",
.description = "Reserve X19",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x2)] = .{
.llvm_name = "reserve-x2",
.description = "Reserve X2",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x20)] = .{
.llvm_name = "reserve-x20",
.description = "Reserve X20",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x21)] = .{
.llvm_name = "reserve-x21",
.description = "Reserve X21",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x22)] = .{
.llvm_name = "reserve-x22",
.description = "Reserve X22",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x23)] = .{
.llvm_name = "reserve-x23",
.description = "Reserve X23",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x24)] = .{
.llvm_name = "reserve-x24",
.description = "Reserve X24",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x25)] = .{
.llvm_name = "reserve-x25",
.description = "Reserve X25",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x26)] = .{
.llvm_name = "reserve-x26",
.description = "Reserve X26",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x27)] = .{
.llvm_name = "reserve-x27",
.description = "Reserve X27",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x28)] = .{
.llvm_name = "reserve-x28",
.description = "Reserve X28",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x29)] = .{
.llvm_name = "reserve-x29",
.description = "Reserve X29",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x3)] = .{
.llvm_name = "reserve-x3",
.description = "Reserve X3",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x30)] = .{
.llvm_name = "reserve-x30",
.description = "Reserve X30",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x31)] = .{
.llvm_name = "reserve-x31",
.description = "Reserve X31",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x4)] = .{
.llvm_name = "reserve-x4",
.description = "Reserve X4",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x5)] = .{
.llvm_name = "reserve-x5",
.description = "Reserve X5",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x6)] = .{
.llvm_name = "reserve-x6",
.description = "Reserve X6",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x7)] = .{
.llvm_name = "reserve-x7",
.description = "Reserve X7",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x8)] = .{
.llvm_name = "reserve-x8",
.description = "Reserve X8",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.reserve_x9)] = .{
.llvm_name = "reserve-x9",
.description = "Reserve X9",
.dependencies = featureSet(&[_]Feature{}),
};
result[@enumToInt(Feature.rvc_hints)] = .{
.llvm_name = "rvc-hints",
.description = "Enable RVC Hint Instructions.",
.dependencies = featureSet(&[_]Feature{}),
};
hit a comptime limitation with computing dense sets
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const ti = @typeInfo(Feature);
for (result) |*elem, i| {
elem.index = i;
elem.name = ti.Enum.fields[i].name;
}
import data from llvm 9
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break :blk result;
Switch CPU/features to simple format
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};
import data from llvm 9
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pub const cpu = struct {
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
2020-02-19 18:30:36 -08:00
pub const baseline_rv32 = CpuModel{
std.Target.CpuFeatures is now a struct with both CPU and feature set Previously it was a tagged union which was one of: * baseline * a specific CPU * a set of features Now, it's possible to have a CPU but also modify the CPU's feature set on top of that. This is closer to what LLVM does. This is more correct because Zig's notion of CPUs (and LLVM's) is not exact CPU models. For example "skylake" is not one very specific model; there are several different pieces of hardware that match "skylake" that have different feature sets enabled.
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.name = "baseline_rv32",
enable behavior and std lib tests for RISC-V 64-bit closes #3338
2020-02-16 21:06:19 -08:00
.llvm_name = null,
std.Target.CpuFeatures is now a struct with both CPU and feature set Previously it was a tagged union which was one of: * baseline * a specific CPU * a set of features Now, it's possible to have a CPU but also modify the CPU's feature set on top of that. This is closer to what LLVM does. This is more correct because Zig's notion of CPUs (and LLVM's) is not exact CPU models. For example "skylake" is not one very specific model; there are several different pieces of hardware that match "skylake" that have different feature sets enabled.
2020-01-22 14:13:31 -08:00
.features = featureSet(&[_]Feature{
.a,
.c,
.d,
.f,
.m,
}),
};
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
2020-02-19 18:30:36 -08:00
pub const baseline_rv64 = CpuModel{
std.Target.CpuFeatures is now a struct with both CPU and feature set Previously it was a tagged union which was one of: * baseline * a specific CPU * a set of features Now, it's possible to have a CPU but also modify the CPU's feature set on top of that. This is closer to what LLVM does. This is more correct because Zig's notion of CPUs (and LLVM's) is not exact CPU models. For example "skylake" is not one very specific model; there are several different pieces of hardware that match "skylake" that have different feature sets enabled.
2020-01-22 14:13:31 -08:00
.name = "baseline_rv64",
enable behavior and std lib tests for RISC-V 64-bit closes #3338
2020-02-16 21:06:19 -08:00
.llvm_name = null,
std.Target.CpuFeatures is now a struct with both CPU and feature set Previously it was a tagged union which was one of: * baseline * a specific CPU * a set of features Now, it's possible to have a CPU but also modify the CPU's feature set on top of that. This is closer to what LLVM does. This is more correct because Zig's notion of CPUs (and LLVM's) is not exact CPU models. For example "skylake" is not one very specific model; there are several different pieces of hardware that match "skylake" that have different feature sets enabled.
2020-01-22 14:13:31 -08:00
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.d,
.f,
.m,
}),
};
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
2020-02-19 18:30:36 -08:00
pub const generic_rv32 = CpuModel{
import data from llvm 9
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.name = "generic_rv32",
enable behavior and std lib tests for RISC-V 64-bit closes #3338
2020-02-16 21:06:19 -08:00
.llvm_name = null,
update target CPUs and features with llvm10's data based on zig-llvm-target-details-generator commit 3aef1b9b4415ed3acfaea4ce8bc233e213548f71
2020-01-30 08:31:41 -08:00
.features = featureSet(&[_]Feature{
.rvc_hints,
}),
import data from llvm 9
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};
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
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pub const generic_rv64 = CpuModel{
import data from llvm 9
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.name = "generic_rv64",
enable behavior and std lib tests for RISC-V 64-bit closes #3338
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.llvm_name = null,
lazily compute the full cpu features dependencies
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.features = featureSet(&[_]Feature{
import data from llvm 9
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.@"64bit",
update target CPUs and features with llvm10's data based on zig-llvm-target-details-generator commit 3aef1b9b4415ed3acfaea4ce8bc233e213548f71
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.rvc_hints,
import data from llvm 9
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}),
};
Switch CPU/features to simple format
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};
import data from llvm 9
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/// All riscv CPUs, sorted alphabetically by name.
/// TODO: Replace this with usage of `std.meta.declList`. It does work, but stage1
/// compiler has inefficient memory and CPU usage, affecting build times.
remove the concept of "sub-architecture" in favor of CPU features. Also rearrange the `std.Target` data structure. * note: `@import("builtin")` was already deprecated in favor of `@import("std").builtin`. * `std.builtin.arch` is now deprecated in favor of `std.builtin.cpu.arch`. * `std.Target.CpuFeatures.Cpu` is now `std.Target.Cpu.Model`. * `std.Target.CpuFeatures` is now `std.Target.Cpu`. * `std.Target` no longer has an `arch` field. Instead it has a `cpu` field, which has `arch`, `model`, and `features`. * `std.Target` no longer has a `cpu_features` field. * `std.Target.Arch` is moved to `std.Target.Cpu.Arch` and it is an enum instead of a tagged union. * `std.Target.parseOs` is moved to `std.Target.Os.parse`. * `std.Target.parseAbi` is moved to `std.Target.Abi.parse`. * `std.Target.parseArchSub` is only for arch now and moved to `std.Target.Cpu.Arch.parse`. * `std.Target.parse` is improved to accept CPU name and features. * `std.Target.Arch.getBaselineCpuFeatures` is moved to `std.Target.Cpu.baseline`. * `std.Target.allCpus` is renamed to `std.Target.allCpuModels`. * `std.Target.defaultAbi` is moved to `std.Target.Abi.default`. * Significant cleanup of aarch64 and arm CPU features, resulting in the needed bit count for cpu feature set going from 174 to 138. * Add `std.Target.Cpu.Feature.Set.addFeatureSet` for merging feature sets together. `-target-feature` and `-target-cpu` are removed in favor of `-mcpu`, to conform to established conventions, and it gains additional power to support cpu features. The syntax is: -mcpu=name+on1+on2-off1-off2 closes #4261
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pub const all_cpus = &[_]*const CpuModel{
std.Target.CpuFeatures is now a struct with both CPU and feature set Previously it was a tagged union which was one of: * baseline * a specific CPU * a set of features Now, it's possible to have a CPU but also modify the CPU's feature set on top of that. This is closer to what LLVM does. This is more correct because Zig's notion of CPUs (and LLVM's) is not exact CPU models. For example "skylake" is not one very specific model; there are several different pieces of hardware that match "skylake" that have different feature sets enabled.
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&cpu.baseline_rv32,
&cpu.baseline_rv64,
import data from llvm 9
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&cpu.generic_rv32,
&cpu.generic_rv64,
Switch CPU/features to simple format
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};