311 lines
9.3 KiB
OCaml
311 lines
9.3 KiB
OCaml
(**************************************************************************)
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(* *)
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(* OCaml *)
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(* *)
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(* Xavier Leroy, projet Gallium, INRIA Rocquencourt *)
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(* Benedikt Meurer, University of Siegen *)
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(* *)
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(* Copyright 2013 Institut National de Recherche en Informatique et *)
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(* en Automatique. *)
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(* Copyright 2012 Benedikt Meurer. *)
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(* *)
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(* All rights reserved. This file is distributed under the terms of *)
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(* the GNU Lesser General Public License version 2.1, with the *)
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(* special exception on linking described in the file LICENSE. *)
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(* *)
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(**************************************************************************)
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(* Description of the ARM processor in 64-bit mode *)
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open Misc
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open Cmm
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open Reg
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open Arch
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open Mach
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(* Instruction selection *)
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let word_addressed = false
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(* Registers available for register allocation *)
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(* Integer register map:
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x0 - x15 general purpose (caller-save)
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x16, x17 temporaries (used by call veeners)
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x18 platform register (reserved)
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x19 - x24 general purpose (callee-save)
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x25 domain state pointer
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x26 trap pointer
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x27 alloc pointer
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x28 alloc limit
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x29 frame pointer
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x30 return address
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sp / xzr stack pointer / zero register
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Floating-point register map:
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d0 - d7 general purpose (caller-save)
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d8 - d15 general purpose (callee-save)
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d16 - d31 general purpose (caller-save)
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*)
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let int_reg_name =
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[| "x0"; "x1"; "x2"; "x3"; "x4"; "x5"; "x6"; "x7";
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"x8"; "x9"; "x10"; "x11"; "x12"; "x13"; "x14"; "x15";
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"x19"; "x20"; "x21"; "x22"; "x23"; "x24";
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"x25"; "x26"; "x27"; "x28"; "x16"; "x17" |]
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let float_reg_name =
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[| "d0"; "d1"; "d2"; "d3"; "d4"; "d5"; "d6"; "d7";
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"d8"; "d9"; "d10"; "d11"; "d12"; "d13"; "d14"; "d15";
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"d16"; "d17"; "d18"; "d19"; "d20"; "d21"; "d22"; "d23";
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"d24"; "d25"; "d26"; "d27"; "d28"; "d29"; "d30"; "d31" |]
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let num_register_classes = 2
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let register_class r =
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match r.typ with
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| Val | Int | Addr -> 0
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| Float -> 1
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let num_available_registers =
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[| 22; 32 |] (* first 22 int regs allocatable; all float regs allocatable *)
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let first_available_register =
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[| 0; 100 |]
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let register_name r =
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if r < 100 then int_reg_name.(r) else float_reg_name.(r - 100)
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let rotate_registers = true
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(* Representation of hard registers by pseudo-registers *)
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let hard_int_reg =
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let v = Array.make 28 Reg.dummy in
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for i = 0 to 27 do
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v.(i) <- Reg.at_location Int (Reg i)
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done;
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v
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let hard_float_reg =
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let v = Array.make 32 Reg.dummy in
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for i = 0 to 31 do
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v.(i) <- Reg.at_location Float (Reg(100 + i))
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done;
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v
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let all_phys_regs =
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Array.append hard_int_reg hard_float_reg
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let phys_reg n =
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if n < 100 then hard_int_reg.(n) else hard_float_reg.(n - 100)
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let reg_x8 = phys_reg 8
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let reg_d7 = phys_reg 107
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let stack_slot slot ty =
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Reg.at_location ty (Stack slot)
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(* Calling conventions *)
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let loc_int last_int make_stack int ofs =
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if !int <= last_int then begin
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let l = phys_reg !int in
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incr int; l
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end else begin
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ofs := Misc.align !ofs size_int;
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let l = stack_slot (make_stack !ofs) Int in
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ofs := !ofs + size_int; l
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end
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let loc_float last_float make_stack float ofs =
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if !float <= last_float then begin
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let l = phys_reg !float in
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incr float; l
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end else begin
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ofs := Misc.align !ofs size_float;
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let l = stack_slot (make_stack !ofs) Float in
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ofs := !ofs + size_float; l
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end
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let loc_int32 last_int make_stack int ofs =
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if !int <= last_int then begin
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let l = phys_reg !int in
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incr int; l
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end else begin
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let l = stack_slot (make_stack !ofs) Int in
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ofs := !ofs + (if macosx then 4 else 8);
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l
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end
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let calling_conventions
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first_int last_int first_float last_float make_stack arg =
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let loc = Array.make (Array.length arg) Reg.dummy in
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let int = ref first_int in
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let float = ref first_float in
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let ofs = ref 0 in
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for i = 0 to Array.length arg - 1 do
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match arg.(i) with
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| Val | Int | Addr ->
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loc.(i) <- loc_int last_int make_stack int ofs
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| Float ->
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loc.(i) <- loc_float last_float make_stack float ofs
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done;
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(loc, Misc.align !ofs 16) (* keep stack 16-aligned *)
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let incoming ofs = Incoming ofs
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let outgoing ofs = Outgoing ofs
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let not_supported _ofs = fatal_error "Proc.loc_results: cannot call"
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(* OCaml calling convention:
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first integer args in r0...r15
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first float args in d0...d15
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remaining args on stack.
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Return values in r0...r15 or d0...d15. *)
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let max_arguments_for_tailcalls = 16
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let last_int_register = if macosx then 7 else 15
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let loc_arguments arg =
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calling_conventions 0 last_int_register 100 115 outgoing arg
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let loc_parameters arg =
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let (loc, _) =
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calling_conventions 0 last_int_register 100 115 incoming arg
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in
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loc
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let loc_results res =
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let (loc, _) =
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calling_conventions 0 last_int_register 100 115 not_supported res
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in
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loc
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(* C calling convention:
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first integer args in r0...r7
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first float args in d0...d7
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remaining args on stack.
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macOS/iOS peculiarity: int32 arguments passed on stack occupy 4 bytes,
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while the AAPCS64 says 8 bytes.
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Return values in r0...r1 or d0. *)
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let external_calling_conventions
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first_int last_int first_float last_float make_stack ty_args =
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let loc = Array.make (List.length ty_args) [| Reg.dummy |] in
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let int = ref first_int in
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let float = ref first_float in
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let ofs = ref 0 in
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List.iteri (fun i ty_arg ->
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begin match ty_arg with
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| XInt | XInt64 ->
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loc.(i) <- [| loc_int last_int make_stack int ofs |]
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| XInt32 ->
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loc.(i) <- [| loc_int32 last_int make_stack int ofs |]
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| XFloat ->
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loc.(i) <- [| loc_float last_float make_stack float ofs |]
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end)
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ty_args;
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(loc, Misc.align !ofs 16) (* keep stack 16-aligned *)
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let loc_external_arguments ty_args =
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external_calling_conventions 0 7 100 107 outgoing ty_args
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let loc_external_results res =
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let (loc, _) = calling_conventions 0 1 100 100 not_supported res in loc
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let loc_exn_bucket = phys_reg 0
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(* See "DWARF for the ARM 64-bit architecture (AArch64)" available from
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developer.arm.com. *)
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let int_dwarf_reg_numbers =
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[| 0; 1; 2; 3; 4; 5; 6; 7;
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8; 9; 10; 11; 12; 13; 14; 15;
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19; 20; 21; 22; 23; 24;
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25; 26; 27; 28; 16; 17;
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|]
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let float_dwarf_reg_numbers =
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[| 64; 65; 66; 67; 68; 69; 70; 71;
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72; 73; 74; 75; 76; 77; 78; 79;
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80; 81; 82; 83; 84; 85; 86; 87;
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88; 89; 90; 91; 92; 93; 94; 95;
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|]
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let dwarf_register_numbers ~reg_class =
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match reg_class with
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| 0 -> int_dwarf_reg_numbers
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| 1 -> float_dwarf_reg_numbers
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| _ -> Misc.fatal_errorf "Bad register class %d" reg_class
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let stack_ptr_dwarf_register_number = 31
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(* Volatile registers: none *)
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let regs_are_volatile _rs = false
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(* Registers destroyed by operations *)
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let destroyed_at_c_call =
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(* x19-x28, d8-d15 preserved *)
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Array.of_list (List.map phys_reg
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[0;1;2;3;4;5;6;7;8;9;10;11;12;13;14;15;
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100;101;102;103;104;105;106;107;
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116;117;118;119;120;121;122;123;
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124;125;126;127;128;129;130;131])
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let destroyed_at_oper = function
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| Iop(Icall_ind _ | Icall_imm _) | Iop(Iextcall { alloc = true; }) ->
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all_phys_regs
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| Iop(Iextcall { alloc = false; }) ->
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destroyed_at_c_call
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| Iop(Ialloc _) ->
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[| reg_x8 |]
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| Iop(Iintoffloat | Ifloatofint | Iload(Single, _) | Istore(Single, _, _)) ->
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[| reg_d7 |] (* d7 / s7 destroyed *)
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| _ -> [||]
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let destroyed_at_raise = all_phys_regs
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let destroyed_at_reloadretaddr = [| |]
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(* Maximal register pressure *)
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let safe_register_pressure = function
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| Iextcall _ -> 8
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| Ialloc _ -> 24
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| _ -> 25
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let max_register_pressure = function
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| Iextcall _ -> [| 10; 8 |]
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| Ialloc _ -> [| 24; 32 |]
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| Iintoffloat | Ifloatofint
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| Iload(Single, _) | Istore(Single, _, _) -> [| 25; 31 |]
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| _ -> [| 25; 32 |]
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(* Pure operations (without any side effect besides updating their result
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registers). *)
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let op_is_pure = function
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| Icall_ind _ | Icall_imm _ | Itailcall_ind _ | Itailcall_imm _
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| Iextcall _ | Istackoffset _ | Istore _ | Ialloc _
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| Iintop(Icheckbound _) | Iintop_imm(Icheckbound _, _)
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| Ispecific(Ishiftcheckbound _) -> false
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| _ -> true
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(* Layout of the stack *)
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let frame_required fd =
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fd.fun_contains_calls
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|| fd.fun_num_stack_slots.(0) > 0
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|| fd.fun_num_stack_slots.(1) > 0
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let prologue_required fd =
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frame_required fd
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(* Calling the assembler *)
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let assemble_file infile outfile =
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Ccomp.command (Config.asm ^ " " ^
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(String.concat " " (Misc.debug_prefix_map_flags ())) ^
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" -o " ^ Filename.quote outfile ^ " " ^ Filename.quote infile)
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let init () = ()
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