132 lines
4.5 KiB
OCaml
132 lines
4.5 KiB
OCaml
(***********************************************************************)
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(* *)
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(* Objective Caml *)
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(* *)
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(* Xavier Leroy, projet Cristal, INRIA Rocquencourt *)
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(* *)
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(* Copyright 1996 Institut National de Recherche en Informatique et *)
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(* en Automatique. All rights reserved. This file is distributed *)
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(* under the terms of the Q Public License version 1.0. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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open Cmm
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open Reg
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open Arch
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open Mach
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open Proc
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open Linearize
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(* (Feeble attempt at) Instruction scheduling for the IA64 *)
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(* Prior to scheduling, we rewrite the code to split reg -> stack
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and stack -> reg moves into two instructions: a "stackaddr" instruction
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that takes the address of the stack variable, and a "spill" or "reload"
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instruction that performs the stack access proper. This way,
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the "stackaddr" instructions can be scheduled earlier. *)
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let temp_counter = ref 0
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let temporaries = [| phys_reg 80 (*r14*); phys_reg 81 (*r15*) |]
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let new_temp () =
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let r = temporaries.(!temp_counter) in
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incr temp_counter;
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if !temp_counter >= Array.length temporaries then temp_counter := 0;
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r
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let rec fixup_stack_accesses i =
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match i.desc with
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Lend -> i
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| Lop(Imove | Ireload | Ispill) ->
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let src = i.arg.(0) and dst = i.res.(0) in
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begin match (src.loc, dst.loc) with
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(Reg _, Reg _) ->
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{ i with next = fixup_stack_accesses i.next }
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| (Stack _, Reg _) ->
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let tmp = new_temp() in
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instr_cons (Lop(Ispecific Istackaddr)) [|src|] [|tmp|]
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(instr_cons (Lop Ireload) [|tmp|] [|dst|]
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(fixup_stack_accesses i.next))
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| (Reg _, Stack _) ->
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let tmp = new_temp() in
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instr_cons (Lop(Ispecific Istackaddr)) [|dst|] [|tmp|]
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(instr_cons (Lop Ispill) [|src; tmp|] [||]
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(fixup_stack_accesses i.next))
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| (_, _) ->
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assert false
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end
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| _ ->
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{ i with next = fixup_stack_accesses i.next }
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(* The basic-block scheduler proper *)
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class scheduler = object (self)
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inherit Schedgen.scheduler_generic as super
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(* Latencies (in cycles). Based on the Itanium, with considerable poetic
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licence. All latencies are tripled in an attempt to favor dual- or
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triple-issue. *)
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(* Most integer operations: 1 cycle --> 3
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Shifts with variable count: 2 cycles --> 6
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Float add, sub, mult, multadd: 5 cycles --> 15
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FP integer multiply: 7 cycles --> 21
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Int loads: 2 cycles --> 6
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Float loads: 9 cycles --> 27
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GP to FP register move: 7 cycles --> 21
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FP to GP register move: 2 cycles --> 6
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*)
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method oper_latency = function
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Ireload -> 6
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| Iload(kind, _) ->
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begin match kind with Single | Double | Double_u -> 27 | _ -> 6 end
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| Iconst_symbol _ -> 6 (* turned into a load *)
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| Iconst_float _ -> 21 (* ends up in a GP to FP register move *)
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| Iintop(Imul) -> 6 (* ends up in a FP to GP register move *)
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| Iintop(Ilsl | Ilsr | Iasr) -> 6
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| Iaddf -> 15
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| Isubf -> 15
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| Imulf -> 15
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| Idivf -> 15
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| Ispecific(Imultaddf | Imultsubf | Isubmultf) -> 15
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| _ -> 3
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(* Issue cycles. Rough approximations. E.g. an operation that expands
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into 2 dependent one-cycle operations is considered to waste 3 issue slots.
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(Depending on the grouping with surrounding instructions, this could
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be as low as 2 or as high as 6.) We adjust upward if the first operation
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has longer latency. *)
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method oper_issue_cycles = function
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Iconst_float _ -> 3
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| Iconst_symbol _ -> 3
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| Iload((Byte_signed | Sixteen_signed | Thirtytwo_signed), _) -> 6
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| Ialloc _ -> 4
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| Iintop(Imul) -> 25
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| Iintop(Icomp _) -> 5
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| Iintop(Icheckbound) -> 3
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| Iintop_imm(Imul, _) -> 12
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| Iintop_imm(Idiv, _) -> 12
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| Iintop_imm(Imod, _) -> 12
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| Iintop_imm(Icheckbound, _) -> 3
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| Idivf -> 24
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| Ifloatofint -> 45
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| Iintoffloat -> 45
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| _ -> 1
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(* Say that Istoreincr terminates a basic block *)
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method oper_in_basic_block = function
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Ispecific(Istoreincr _) -> false
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| op -> super#oper_in_basic_block op
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end
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let schedule_fundecl = (new scheduler)#schedule_fundecl
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let fundecl f =
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schedule_fundecl {f with fun_body = fixup_stack_accesses f.fun_body}
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