90 lines
3.0 KiB
ArmAsm
90 lines
3.0 KiB
ArmAsm
/**************************************************************************/
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/* */
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/* OCaml */
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/* */
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/* Nicolas Ojeda Bar <n.oje.bar@gmail.com> */
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/* */
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/* Copyright 2019 Institut National de Recherche en Informatique et */
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/* en Automatique. */
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/* */
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/* All rights reserved. This file is distributed under the terms of */
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/* the GNU Lesser General Public License version 2.1, with the */
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/* special exception on linking described in the file LICENSE. */
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/* */
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/**************************************************************************/
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#define STORE sd
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#define LOAD ld
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.globl call_gen_code
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.align 2
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call_gen_code:
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/* Set up stack frame and save callee-save registers */
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ADDI sp, sp, -208
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STORE ra, 192(sp)
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STORE s0, 0(sp)
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STORE s1, 8(sp)
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STORE s2, 16(sp)
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STORE s3, 24(sp)
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STORE s4, 32(sp)
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STORE s5, 40(sp)
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STORE s6, 48(sp)
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STORE s7, 56(sp)
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STORE s8, 64(sp)
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STORE s9, 72(sp)
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STORE s10, 80(sp)
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STORE s11, 88(sp)
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fsd fs0, 96(sp)
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fsd fs1, 104(sp)
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fsd fs2, 112(sp)
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fsd fs3, 120(sp)
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fsd fs4, 128(sp)
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fsd fs5, 136(sp)
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fsd fs6, 144(sp)
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fsd fs7, 152(sp)
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fsd fs8, 160(sp)
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fsd fs9, 168(sp)
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fsd fs10, 176(sp)
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fsd fs11, 184(sp)
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/* Shuffle arguments */
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mv t0, a0
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mv a0, a1
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mv a1, a2
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mv a2, a3
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mv a3, a4
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/* Call generated asm */
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jalr t0
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/* Reload callee-save registers and return address */
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LOAD ra, 192(sp)
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LOAD s0, 0(sp)
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LOAD s1, 8(sp)
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LOAD s2, 16(sp)
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LOAD s3, 24(sp)
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LOAD s4, 32(sp)
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LOAD s5, 40(sp)
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LOAD s6, 48(sp)
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LOAD s7, 56(sp)
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LOAD s8, 64(sp)
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LOAD s9, 72(sp)
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LOAD s10, 80(sp)
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LOAD s11, 88(sp)
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fld fs0, 96(sp)
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fld fs1, 104(sp)
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fld fs2, 112(sp)
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fld fs3, 120(sp)
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fld fs4, 128(sp)
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fld fs5, 136(sp)
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fld fs6, 144(sp)
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fld fs7, 152(sp)
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fld fs8, 160(sp)
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fld fs9, 168(sp)
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fld fs10, 176(sp)
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fld fs11, 184(sp)
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addi sp, sp, 208
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ret
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.globl caml_c_call
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.align 2
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caml_c_call:
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jr t2
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