5401ce8473
Update headers for the new license.
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Remains to be done: remove all headers in testsuite/tests.
2016-02-18 16:59:16 +01:00
ee8f71101b
clean up whitespace and cut long lines
2016-02-17 13:36:27 +01:00
05f1746cb5
Rename to max_arguments_for_tailcalls; revise numbers assuming no unboxed floats using the OCaml calling conventions
2016-02-08 15:02:40 +01:00
b5618e8642
max_arguments_without_passing_on-stack
2016-01-29 15:57:36 +00:00
8538e9e179
Fix fallout from GPR#360 on other backends
2016-01-12 19:24:56 +01:00
098e69aa66
Add notes and pointers to reference documents for each ocamlopt architecture.
2015-12-20 12:48:28 +01:00
6cd8656249
PR#7024 and GPR#295: CSE confuses +0.0 and -0.0
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The fix consists in representing float literals by their bit patterns (int64) in the Mach and Linear intermediate languages.
A regression test was added to the test suite.
2015-11-19 09:25:02 +01:00
d813aea23b
Remove dead code.
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git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16516 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-10-16 17:04:56 +00:00
cf9002cfd8
PR#6979: better code generation in x86-32 backend for copying floats to the stack (Marc Lasson, review by Xavier Leroy).
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git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16414 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-09-10 09:47:37 +00:00
1d196f4ddd
Support [@unboxed] and [@untagged] attributes
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Adding [@unboxed] (resp [@untagged]) on a primitive argument means
that the argument must passed unboxed (resp untagged) to the external
function. Adding [@unboxed] (resp [@untagged]) on the result means
that the external function returns its result unboxed (resp untagged).
The unboxing (resp untagging) method is derived from the type.
Currently unboxing is suported for: float, int32, int64 and nativeint.
Untagging is supported for int.
This patch also increases the cm{i,o,a,x,xa} magic numbers as the type
Primitive.description is changed.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16382 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-25 16:18:46 +00:00
b71ce51227
Hopefully finish 16278 (again).
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git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16281 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-27 16:48:32 +00:00
2b25dd5d4a
Hopefully finish 16278.
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git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16280 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-27 16:35:28 +00:00
7027b858eb
Update "register_class" followign the introduction of the Val machine type.
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git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16278 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-27 11:37:52 +00:00
09428028b1
More precise typing at the C-- and Mach level.
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(Merge of branch cmm-mach-types and PR#115.)
- Register type "Addr" is split into
. "Val" (well-formed OCaml values, appropriate as GC roots)
. "Addr" (derived pointers within the heap, must not survive a GC)
- memory_chunk "Word" is split into
. "Word_val" (OCaml value)
. "Word_int" (native-sized integer, not a pointer into the heap)
Cmmgen was updated to use Word_val or Word_int as appropriate.
Application #1 : fail at compile-time if a derived pointer within the heap
survives a GC point (cf. PR#6484).
Application #2 : CSE can do a better job across allocation points
(keep factoring expressions of type Int, Val, Float, but not Addr).
Application #3 : slightly fewer roots given to the GC
(e.g. pointers into bigarray data).
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16269 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-27 09:20:39 +00:00
53231bcdc3
Update to trunk r16267.
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A change on trunk in cmmgen was causing problems: the use of array_indexing
in bigarray_indexing was constructing derived pointers of Addr type
instead of the correct Int type. (Because bigarray inner pointers
are outside the heap, and because they are live across allocations.)
Added an optional argument to array_indexing to specify expected
pointer type, and adapted bigarray_indexing to use it with type Int.
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/cmm-mach-types@16268 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-27 08:18:53 +00:00
27a2bd3e16
Adapt 32-bit emit.mlp to curried style.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15614 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-11-27 17:29:49 +00:00
9decba7731
Rename Intel_* to X86_*.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15612 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-11-27 17:12:21 +00:00
ac02f56351
More precise typing at the C-- and Mach level:
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- Register type "Addr" is split into
. "Val" (well-formed OCaml values, appropriate as GC roots)
. "Addr" (derived pointers within the heap, must not survive a GC)
- memory_chunk "Word" is split into
. "Word_val" (OCaml value)
. "Word_int" (native-sized integer, not a pointer into the heap)
Cmmgen was updated to use Word_val or Word_int as appropriate.
Application #1 : fail at compile-time if a derived pointer within the heap
survives a GC point (cf. PR#6484).
Application #2 : CSE can do a better job across allocation points
(keep factoring expressions of type Int, Val, Float, but not Addr).
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/cmm-mach-types@15568 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-11-06 08:54:14 +00:00
cf2cdb9fc1
Typos.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15447 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-10-03 12:48:45 +00:00
3b6f79b288
Get rid of warning attribute.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15402 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 15:08:18 +00:00
cf495ee713
Inline inner DSL module.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15401 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 15:07:29 +00:00
0fd13b09d7
Get rid of End directive (hard-code in masm backend).
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15400 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 15:03:02 +00:00
8e12390dd5
ascii -> bytes
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15399 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 15:00:52 +00:00
493b049c59
llabel -> label
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15398 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:59:56 +00:00
2a66b9f4fd
Adapt 32-bit backend as well.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15397 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:59:11 +00:00
4e4eaa624b
Fix.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15395 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:46:19 +00:00
48ae8d422e
Merge DSL32 and DSL64.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15394 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:45:35 +00:00
56c045db01
Cleanup.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15393 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:41:41 +00:00
15ffda9671
Cleanup.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15392 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:40:09 +00:00
180d759cd4
Getting rid of instruction suffixes. Finish, merge INS, INS32, INS64, get rid of duplicates.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15391 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:37:09 +00:00
f69748eed4
Getting rid of instruction suffixes: step 3, using pure Intel mnemonics for the 32-bit backend.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15390 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-30 14:27:23 +00:00
c06bad85ea
Fix.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15367 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-29 13:42:28 +00:00
79fe0be8ad
Avoid duplication in register names.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15366 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-29 13:39:01 +00:00
d4affdb259
Rename NO -> NONE.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15354 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-26 16:11:54 +00:00
fc4e2cd892
Cleanup.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15330 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-24 16:03:17 +00:00
51472c925c
Cleanup.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15328 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-24 15:53:26 +00:00
7dea33dc40
Cosmetic, bringing i386 and amd64 versions of emit.mlp closer to each other.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15326 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-24 10:28:28 +00:00
6bbc2d7a51
Textual emitters are responsible for emitting the whole file.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15302 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-23 08:36:45 +00:00
237406042b
Represent the current location explicitly, not through gas encoding (special dot symbol).
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15296 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-22 14:56:33 +00:00
80e8e2c24f
Do not keep data_size with integer constants.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15294 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-22 14:47:30 +00:00
4f4596d77c
Represent symbol addresses in a uniform way in the AST. The instruction emitter decides the interpret them as absolute or relative addresses.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15287 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-22 11:51:53 +00:00
ff1e7afbb6
Fix.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15286 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-22 11:39:39 +00:00
84e9598fc3
Simplify.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15285 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-22 11:37:53 +00:00
78445243b6
Split immediate symbol and immediate constant cases.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15284 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-22 11:35:50 +00:00
043f5ee94c
Cosmetic.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15252 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-17 15:57:13 +00:00
4d37044592
Fix discrepency with trunk's emit.mlp.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15251 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-17 15:48:39 +00:00
5577142100
Drop instruction suffix for some unary x87 instructions; switch from 'force' to 'check' terminology; define a proper type for 32-bit x86 registers.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15250 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-17 15:41:55 +00:00
3a13ba6c04
Do not keep the prehistoric gas bug on fsub/fsubrp/fdiv/fdivrp in the DSL. Manage it purely in Intel_gas.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15249 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-17 12:58:43 +00:00
4b002b1818
Cleanup. The align directive in the AST is normalized to the usual semantics. The different treatment for OSX is located in Intel_gas.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15247 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-17 12:41:35 +00:00
8609a7821a
Continue.
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git-svn-id: http://caml.inria.fr/svn/ocaml/branches/abstract_intel_emit@15242 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2014-09-17 09:07:51 +00:00
Damien Doligez
Mark Shinwell
Mark Shinwell
Xavier Leroy
Alain Frisch
Jérémie Dimino