Commit Graph

98 Commits (master)

Author SHA1 Message Date
Nicolás Ojeda Bär 43883ae4bc Remove labels after calls, checkbound, and GC points 2020-10-08 20:28:15 +02:00
Greta Yorsh 2bb2bde74c
Prologue size should not depend on stack_offset (power, arm64) (#9083)
* Prologue size does not depend on stack_offset (power, arm64)

Define `initial_stack_offset` of a function, independently
of stack_offset, and use it to compute both frame_size and
prologue_size.
2020-09-03 13:26:00 +02:00
Stephen Dolan 7fe360401b Per-architecture support for allocation size info in frame tables.
amd64: remove caml_call_gc{1,2,3} and simplify caml_alloc{1,2,3,N}
       by tail-calling caml_call_gc.

i386:  simplify caml_alloc{1,2,3,N} by tail-calling caml_call_gc.
       these functions do not need to preserve ebx.

arm:   simplify caml_alloc{1,2,3,N} by tail-calling caml_call_gc.
       partial revert of #8619.

arm64: simplify caml_alloc{1,2,3,N} by tail-calling caml_call_gc.
       partial revert of #8619.

power: partial revert of #8619.
       avoid restarting allocation sequence after failure.

s390:  partial revert of #8619.
       avoid restarting allocation seqeunce after failure.
2019-10-23 09:24:13 +01:00
Stephen Dolan 768dcce48f Use allocation-size info on more than just amd64.
Moves the alloc_dbginfo type to Debuginfo, to avoid a circular
dependency on architectures that use Branch_relaxation.

This commit generates frame tables with allocation sizes on all
architectures, but does not yet update the allocation code for
non-amd64 backends.
2019-10-22 11:47:31 +01:00
Greta Yorsh aeebb62e9b Move contains_calls and num_stack_slots from Proc to Mach.fundecl 2019-09-09 11:33:03 +01:00
Greta Yorsh 0b6b544fcb Split Linearize into two modules
Separate the description of the IR from the transformations
performed on it by moving type declarations from linearize.ml
into their own file, called linear.ml.
2019-09-04 11:55:11 +01:00
KC Sivaramakrishnan 4dab86ad54 Fix domain state field offset for power (32-bit)
The domain state fields are always aligned at 8 byte offset. This is to
ensure that even on a 32-bit where pointers are 32-bits and doubles are
64-bits, the offset calculation remains the same as 64-bit
architectures.
2019-08-23 09:50:05 +05:30
KC Sivaramakrishnan f7920a127f Domain state works on Power64 2019-08-23 09:50:05 +05:30
Greta Yorsh d8b6a1713b Add pseudo-instruction `Ladjust_trap_depth` (#2322)
Ladjust_trap_depth replaces dummy Lpushtrap generated in linearize of
Iexit to notify assembler generation about updates to the
stack. Ladjust_trap_depth is used to keep the virtual stack pointer in
sync and emit dwarf information, without emitting any assembly
instructions. It therefore avoids generating dead code.

This patch is extract from PR1482 @lthls
2019-06-24 14:18:37 +01:00
Stephen Dolan c24e5b5c8a Ensure that Gc.minor_words remains accurate after a GC (#8619)
If an allocation fails, the decrement of young_ptr should be undone
before the GC is entered. This happened correctly on bytecode but not
on native code.

This commit (squash of pull request #8619) fixes it for all the
platforms supported by ocamlopt.

amd64: add alternate entry points caml_call_gc{1,2,3} for code size
optimisation.

powerpc: introduce one GC call point per allocation size per function.
Each call point corrects the allocation pointer r31 before calling
caml_call_gc.

i386, arm, arm64, s390x: update the allocation pointer after the
conditional branch to the GC, not before.

arm64: simplify the code generator: Ialloc can assume that less than
0x1_0000 bytes are allocated, since the max allocation size for the
minor heap is less than that.

This is a partial cherry-pick of commit 8ceec on multicore.
2019-05-04 10:01:23 +02:00
Xavier Leroy 10994d8c80
Ensure frame table is 8-aligned on ARM64 and PPC64 (#8557)
This is a follow-up to commit 7077b60 that fixed a lack of 8-alignment for the frame table on ADM64, as reported in #7591.
A similar issue was reported in #7887 for ARM64 and is fixed here.
For good measure, explicit alignment was added  to PPC64 as well, although there was probably no issue there.

Closes: #7887.
2019-03-29 15:31:21 +01:00
Mark Shinwell 4334b2de87
Position [Lprologue] correctly (#2292) 2019-03-29 11:47:53 +00:00
Mark Shinwell 0933593596 Fix ppc64 TOC load for exception handler addresses (#8506)
The address was loaded from the TOC into register r0.  This generated  bad code in the "big TOC" case, as r0 was used as index register.  The fix is to use another temporary register instead of r0.
Add "arch_power" builtin to ocamltest.
Add test case.
2019-03-18 13:31:57 +01:00
Mark Shinwell 2cc1ea26b9 Remove gprof support (#2314)
This commit removes support for gprof-based profiling (the -p option to ocamlopt).  It follows a discussion on the core developers' list, which indicated that removing gprof support was a reasonable thing to do. The rationale is that there are better easy-to-use profilers out there now, such as perf for Linux and Instruments on macOS; and the gprof support has always been patchy across targets. We save a whole build of the runtime and simplify some other parts of the codebase by removing it.
2019-03-16 19:56:53 +01:00
Vincent Laviron 1dba5329a2 Linearize: for Trywith, remove the jump/call to the handler (#2237) 2019-03-07 10:37:22 +00:00
Mark Shinwell dae65dacda
Rename Mach.Ialloc record field from _words_ to _bytes_ and fix logic in a couple of places (#2074) 2018-10-02 16:00:03 +01:00
Mark Shinwell 2a072d8036
Add Lprologue (#2055) 2018-09-24 10:03:26 +01:00
Sébastien Hinderer d3e73595e5 Merge the asmrun and byterun directories into the runtime directory 2018-06-28 17:50:33 +02:00
Leo White 1671e5a3af Treat negated float comparisons more directly (#1487)
* Add float comparison test

* Treat negated float comparisons more directly

* Add Changes entry
2018-02-28 14:19:46 +01:00
Mark Shinwell 39f4f4e931 Add a padding word before "data_end" symbols (MPR#6329) (#1437) 2017-10-24 16:57:20 +01:00
Mark Shinwell b65096678b Register availability analysis (#856) 2017-09-15 11:08:14 +01:00
Xavier Leroy 24980d3fd9 Generate frametable in data section to improve code relocatability
The frametable contains absolute pointers into the code, which require relocation in shared libraries and also in position-independent executables (PIE).

Before this commit, the frametable was put in the readonly data section (rodata), which is part of the text segment.  In shared libraries and PIEs, relocations in the text segment are undesirable (they make the text segment writable, at least temporarily) and are flagged as warnings or errors by various tools (Debian's lintian package checker; the --warn-shared-textrel option of GNU ld; etc).

This commit puts the frametable in the (read-write) data section (.data), like in the AMD64 port for example.  In PowerPC 64-bit mode, this is enough to produce .so files and PIE executables that contain no relocations in the text segment.

In PowerPC 32-bit mode there remains relocations in the text segment, but that was expected because the code we generate is not position-independent (PIC).
2017-09-07 12:17:03 +02:00
KC Sivaramakrishnan abc5360dc1 Remove duplicate live_offset entries from frametables (#453) 2016-12-09 15:41:22 +00:00
Mark Shinwell cd0bd8aa73 Spacetime: a new memory profiler (#585) 2016-07-29 15:07:10 +01:00
François Bobot bb4a1b4f5d Specialize raise_kind after cmmgen
since the semantic changed. There is no need to check Clflags.debug
   anymore Raise_withtrace, means that traces must be computed (if the
   runtime boolean is true).
2016-07-28 15:29:50 +02:00
François Bobot 7be0a81e9c Fix backtrace for regular raise on arm64, arm
for constant exception, a reraise was done
    instead of a raise
2016-07-28 13:46:23 +02:00
Gabriel Scherer 99db3207e7 fallout from #645: remove emit_data_label (unused, breaks the build) 2016-07-10 10:14:40 -04:00
Alain Frisch e3ee2805b7 Merge pull request #645 from mshinwell/delete_cmm_label_stuff
Remove Cdefine_label and Clabel_address
2016-07-10 14:52:07 +02:00
Mark Shinwell 5f00ce793e Improve location handling in the middle end (version for merging) (#666) 2016-07-06 15:42:29 +01:00
Mark Shinwell c843ca0691 Labels after calls, call GC points and checkbound points (again) (#660) 2016-07-06 11:44:00 +01:00
Mark Shinwell 8e16cdd85d Remove Cdefine_label and Clabel_address 2016-06-29 10:01:03 +01:00
Fabrice Le Fessant 80c4576f03 Add line directives to preprocessed files 2016-06-29 10:43:00 +02:00
Xavier Leroy 5d02ca6f28 In frame tables, distinguish data pointers from code pointers
Since GPR#247 (stack backtraces aware of inlining) was merged, frame tables contain two kinds of addresses of labels: code labels (as before) and data labels (new, pointing to sub-frames).

On ARM in Thumb mode, the two kinds of pointers must be distinguished, because pointers to Thumb code have the low bit set, and the assembler needs to know whether a label denotes code or data to set the low bit or not.

This commit fixes this problem by splitting the "efa_label" action of record Emitaux.emit_frame_actions into two actions, "efa_code_label" and "efa_data_label".  On all ports except ARM, the two actions are identical.  On ARM, the actions add the appropriate ".type" declaration.

Tested on ARM-32 and x86-64 only.  CI will test the other platforms.
2016-06-27 09:14:54 +02:00
alainfrisch 502e4f9336 More warnings when compiling the compiler. 2016-03-15 22:46:35 +01:00
Damien Doligez 5401ce8473 Update headers for the new license.
Remains to be done: remove all headers in testsuite/tests.
2016-02-18 16:59:16 +01:00
Xavier Leroy eef84c432a PR#7037: don't put temporary asm file names into object files.
This way, builds are reproducible.
2015-12-13 18:40:04 +01:00
Xavier Leroy 6cd8656249 PR#7024 and GPR#295: CSE confuses +0.0 and -0.0
The fix consists in representing float literals by their bit patterns (int64) in the Mach and Linear intermediate languages.

A regression test was added to the test suite.
2015-11-19 09:25:02 +01:00
Xavier Leroy 6d14fe58f2 Pull request #258: more precise computation of instruction sizes, esp. with respect to big TOCs.
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16514 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-10-16 15:12:56 +00:00
Damien Doligez b860d63145 whitespace cleanup, cut long lines, add some missing headers
git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16415 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-09-11 11:58:31 +00:00
Xavier Leroy 61a49e9a01 Reset debugging information at the beginning of every module.
Fix a tab.


git-svn-id: http://caml.inria.fr/svn/ocaml/trunk@16376 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-25 13:52:59 +00:00
Xavier Leroy e64461246f Typo in comment explaining the TOC galore. (Courtesy M. Shinwell.)
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16363 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-21 12:36:45 +00:00
Xavier Leroy bcb02e89d4 Select 32-bit TOC model if compiling with -for-pack
ocamlopt -pack can create large .o files that can easily overflow the 16-bit TOC model.


git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16342 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-07 15:17:36 +00:00
Xavier Leroy 7426611bae Force word-alignment of static OCaml data.
On a Power7/RHEL6.4 machine, misalignment of the .data section was observed.


git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16341 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-06 14:39:35 +00:00
Xavier Leroy 7dacc03db0 PPC64 ABI v1: not enough space was reserved for the parameter save area before calls to C functions.
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16339 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-06 12:32:30 +00:00
Xavier Leroy cf87a2c664 Update wrt trunk r16319.
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16320 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-08-03 09:18:04 +00:00
Xavier Leroy f3fcf87a53 Support for gprof profiling (ocamlopt -p)
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16301 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-31 10:58:53 +00:00
Xavier Leroy 2917610b83 Wrong cfi_adjust_cfa_offset directive was generated.
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16300 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-30 13:46:23 +00:00
Xavier Leroy d232e7d4ff PPC64 little-endian support.
git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16298 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-30 09:07:09 +00:00
Xavier Leroy a8d15c866b - Use addis/addi in preference to addis/ori to enable instruction fusion
on POWER8.
- PPC64: concatenate jump tables so as to reduce the number of TOC entries
  for jump table labels.
- Use simpler asm directives for filling the TOC.


git-svn-id: http://caml.inria.fr/svn/ocaml/branches/ppc64@16297 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-30 08:54:22 +00:00
Xavier Leroy 53231bcdc3 Update to trunk r16267.
A change on trunk in cmmgen was causing problems: the use of array_indexing
in bigarray_indexing was constructing derived pointers of Addr type
instead of the correct Int type.  (Because bigarray inner pointers
are outside the heap, and because they are live across allocations.)
Added an optional argument to array_indexing to specify expected
pointer type, and adapted bigarray_indexing to use it with type Int.


git-svn-id: http://caml.inria.fr/svn/ocaml/branches/cmm-mach-types@16268 f963ae5c-01c2-4b8c-9fe0-0dff7051ff02
2015-07-27 08:18:53 +00:00