1995-08-09 08:06:35 -07:00
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(***********************************************************************)
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(* *)
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(* Caml Special Light *)
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(* *)
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(* Xavier Leroy, projet Cristal, INRIA Rocquencourt *)
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(* *)
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(* Copyright 1995 Institut National de Recherche en Informatique et *)
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(* Automatique. Distributed only by permission. *)
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(* *)
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(***********************************************************************)
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(* $Id$ *)
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1995-06-15 01:17:29 -07:00
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(* Processor descriptions *)
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(* The Use_default exception is raised by the selection and reloading
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functions to signal cases they don't handle *)
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exception Use_default
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(* Instruction selection *)
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val select_addressing:
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Cmm.expression -> Arch.addressing_mode * Cmm.expression
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val select_oper:
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Cmm.operation -> Cmm.expression list ->
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1995-07-02 09:41:48 -07:00
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Mach.operation * Cmm.expression list
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val select_store:
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Arch.addressing_mode -> Cmm.expression -> Mach.operation * Cmm.expression
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1995-06-15 01:17:29 -07:00
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val pseudoregs_for_operation:
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Mach.operation -> Reg.t array -> Reg.t array ->
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Reg.t array * Reg.t array
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val is_immediate: int -> bool
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1995-07-25 04:37:38 -07:00
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val word_addressed: bool
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1995-06-15 01:17:29 -07:00
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(* Registers available for register allocation *)
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val num_register_classes: int
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val register_class: Reg.t -> int
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val num_available_registers: int array
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val first_available_register: int array
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val register_name: int -> string
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val phys_reg: int -> Reg.t
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(* Calling conventions *)
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val loc_arguments: Reg.t array -> Reg.t array * int
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val loc_results: Reg.t array -> Reg.t array
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val loc_parameters: Reg.t array -> Reg.t array
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val loc_external_arguments: Reg.t array -> Reg.t array * int
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val loc_external_results: Reg.t array -> Reg.t array
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val loc_exn_bucket: Reg.t
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1995-07-02 09:41:48 -07:00
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(* Maximal register pressures for pre-spilling *)
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1995-07-10 02:48:27 -07:00
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val safe_register_pressure: Mach.operation -> int
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val max_register_pressure: Mach.operation -> int array
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1995-07-02 09:41:48 -07:00
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1995-06-15 01:17:29 -07:00
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(* Registers destroyed by operations *)
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val destroyed_at_oper: Mach.instruction_desc -> Reg.t array
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val destroyed_at_raise: Reg.t array
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(* Reloading of instruction arguments, storing of instruction results *)
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1995-07-02 09:41:48 -07:00
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val reload_test:
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(Reg.t -> Reg.t) -> Mach.test -> Reg.t array -> Reg.t array
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1995-06-15 01:17:29 -07:00
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val reload_operation:
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(Reg.t -> Reg.t) -> Mach.operation -> Reg.t array -> Reg.t array ->
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Reg.t array * Reg.t array
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1995-08-13 02:31:50 -07:00
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(* Latency info for instruction scheduling *)
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val need_scheduling: bool
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val oper_latency: Mach.operation -> int
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1995-07-07 09:14:06 -07:00
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(* Info for laying out the stack frame *)
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1995-06-15 01:17:29 -07:00
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val num_stack_slots: int array
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val contains_calls: bool ref
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1995-07-02 09:41:48 -07:00
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1995-07-11 11:03:29 -07:00
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(* Calling the assembler and the archiver *)
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1995-07-02 09:41:48 -07:00
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val assemble_file: string -> string -> int
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1995-07-11 11:03:29 -07:00
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val create_archive: string -> string list -> int
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