1997-07-24 04:49:12 -07:00
|
|
|
(***********************************************************************)
|
|
|
|
(* *)
|
|
|
|
(* Objective Caml *)
|
|
|
|
(* *)
|
|
|
|
(* Xavier Leroy, projet Cristal, INRIA Rocquencourt *)
|
|
|
|
(* *)
|
|
|
|
(* Copyright 1997 Institut National de Recherche en Informatique et *)
|
1999-11-17 10:59:06 -08:00
|
|
|
(* en Automatique. All rights reserved. This file is distributed *)
|
|
|
|
(* under the terms of the Q Public License version 1.0. *)
|
1997-07-24 04:49:12 -07:00
|
|
|
(* *)
|
|
|
|
(***********************************************************************)
|
|
|
|
|
|
|
|
(* $Id$ *)
|
|
|
|
|
|
|
|
(* Instruction scheduling *)
|
|
|
|
|
|
|
|
type code_dag_node =
|
|
|
|
{ instr: Linearize.instruction;
|
|
|
|
delay: int;
|
|
|
|
mutable sons: (code_dag_node * int) list;
|
|
|
|
mutable date: int;
|
|
|
|
mutable length: int;
|
|
|
|
mutable ancestors: int;
|
|
|
|
mutable emitted_ancestors: int }
|
|
|
|
|
1998-06-24 12:22:26 -07:00
|
|
|
class virtual scheduler_generic : object
|
1997-07-24 04:49:12 -07:00
|
|
|
(* Can be overriden by processor description *)
|
1998-06-24 12:22:26 -07:00
|
|
|
method virtual oper_issue_cycles : Mach.operation -> int
|
1997-07-24 04:49:12 -07:00
|
|
|
(* Number of cycles needed to issue the given operation *)
|
1998-06-24 12:22:26 -07:00
|
|
|
method virtual oper_latency : Mach.operation -> int
|
1997-07-24 04:49:12 -07:00
|
|
|
(* Number of cycles needed to complete the given operation *)
|
1998-04-27 02:56:13 -07:00
|
|
|
method reload_retaddr_issue_cycles : int
|
|
|
|
(* Number of cycles needed to issue a Lreloadretaddr operation *)
|
|
|
|
method reload_retaddr_latency : int
|
|
|
|
(* Number of cycles needed to complete a Lreloadretaddr operation *)
|
1997-07-24 04:49:12 -07:00
|
|
|
method oper_in_basic_block : Mach.operation -> bool
|
|
|
|
(* Says whether the given operation terminates a basic block *)
|
1998-04-27 02:56:13 -07:00
|
|
|
method is_store : Mach.operation -> bool
|
|
|
|
(* Says whether the given operation is a memory store *)
|
|
|
|
method is_load : Mach.operation -> bool
|
|
|
|
(* Says whether the given operation is a memory load *)
|
1998-10-19 10:21:45 -07:00
|
|
|
method is_checkbound : Mach.operation -> bool
|
|
|
|
(* Says whether the given operation is a checkbound *)
|
1997-07-24 04:49:12 -07:00
|
|
|
(* Entry point *)
|
|
|
|
method schedule_fundecl : Linearize.fundecl -> Linearize.fundecl
|
|
|
|
end
|