From acdf48a2931c774e61b77a6211f7bb102c24611d Mon Sep 17 00:00:00 2001
From: ademant <ademant@gmx.de>
Date: Tue, 4 Jun 2019 05:30:58 +0200
Subject: [PATCH] integrate vedirect

---
 tri.py      | 98 +++++++++++++++++++++++++++++++++++++++++++++++++----
 vedirect.py |  1 +
 2 files changed, 92 insertions(+), 7 deletions(-)

diff --git a/tri.py b/tri.py
index 554c429..37a5468 100755
--- a/tri.py
+++ b/tri.py
@@ -1,12 +1,92 @@
 #!/usr/bin/env python
 
-import time
 import numpy as np
-import socket
-import sys
-import json
-import smbus2
-import bme280
+import os, serial,time,socket,sys,json,smbus2,bme280
+
+# import vedirect from https://github.com/karioja/vedirect
+class vedirect:
+    def __init__(self, serialport, timeout):
+        self.serialport = serialport
+        self.ser = serial.Serial(serialport, 19200, timeout=timeout)
+        self.header1 = '\r'
+        self.header2 = '\n'
+        self.hexmarker = ':'
+        self.delimiter = '\t'
+        self.key = ''
+        self.value = ''
+        self.bytes_sum = 0;
+        self.state = self.WAIT_HEADER
+        self.dict = {}
+    (HEX, WAIT_HEADER, IN_KEY, IN_VALUE, IN_CHECKSUM) = range(5)
+    def input(self, byte):
+        if byte == self.hexmarker and self.state != self.IN_CHECKSUM:
+            self.state = self.HEX
+        if self.state == self.WAIT_HEADER:
+            self.bytes_sum += ord(byte)
+            if byte == self.header1:
+                self.state = self.WAIT_HEADER
+            elif byte == self.header2:
+                self.state = self.IN_KEY
+            return None
+        elif self.state == self.IN_KEY:
+            self.bytes_sum += ord(byte)
+            if byte == self.delimiter:
+                if (self.key == 'Checksum'):
+                    self.state = self.IN_CHECKSUM
+                else:
+                    self.state = self.IN_VALUE
+            else:
+                self.key += byte
+            return None
+        elif self.state == self.IN_VALUE:
+            self.bytes_sum += ord(byte)
+            if byte == self.header1:
+                self.state = self.WAIT_HEADER
+                self.dict[self.key] = self.value;
+                self.key = '';
+                self.value = '';
+            else:
+                self.value += byte
+            return None
+        elif self.state == self.IN_CHECKSUM:
+            self.bytes_sum += ord(byte)
+            self.key = ''
+            self.value = ''
+            self.state = self.WAIT_HEADER
+            if (self.bytes_sum % 256 == 0):
+                self.bytes_sum = 0
+                return self.dict
+            else:
+                print 'Malformed packet'
+                self.bytes_sum = 0
+        elif self.state == self.HEX:
+            self.bytes_sum = 0
+            if byte == self.header2:
+                self.state = self.WAIT_HEADER
+        else:
+            raise AssertionError()
+    def read_data(self):
+        while True:
+            byte = self.ser.read(1)
+            packet = self.input(byte)
+    def read_data_single(self):
+        while True:
+            byte = self.ser.read(1)
+            packet = self.input(byte)
+            if (packet != None):
+                return packet
+    def read_data_callback(self, callbackFunction):
+        while True:
+            byte = self.ser.read(1)
+            if byte:
+                packet = self.input(byte)
+                if (packet != None):
+                    callbackFunction(packet)
+            else:
+                break
+def print_data_callback(data):
+    print data
+# end import vedirect
 
 a = 2
 # host and port of logging server
@@ -31,6 +111,9 @@ log.setLevel(logging.ERROR)
 client = ModbusClient(method='rtu', port='/dev/ttyUSB0', baudrate=9600, timeout=1)
 client.connect()
 
+# declare ve mppt
+ve=vedirect('/dev/serial/by-id/usb-VictronEnergy_BV_VE_Direct_cable_VE1SSBVT-if00-port0',60)
+
 # declare adc
 adc = ADS1115()
 adcc = ADS1115(address=0x49, busnum=1)
@@ -39,7 +122,8 @@ GAIN = 1
 # declare vars
 channel_names=["time","CPU_temp","a0_0","a0_1","a0_2","a0_3","a1_0","a1_1","a1_2","a1_3","volt_scale","amp_scale",
   "volt_bat_term","volt_bat_sens","volt_arr","amp_bat","amp_arr","temp_heatsink","temp_bat","ah_res",
-  "ah_tot","kwh_res","kwh_tot","watt_in","watt_out","hour_tot","state","volt_sweep_mp","volt_sweep_oc","temperature","pressure","humidity"]
+  "ah_tot","kwh_res","kwh_tot","watt_in","watt_out","hour_tot","state","volt_sweep_mp","volt_sweep_oc",
+  "temperature","pressure","humidity","volt_bat_ve","volt_arr_ve","amp_ve"]
 ch_val=np.zeros(len(channel_names))
 for i in range(len(channel_names)):
 	ch_val[i]=(-1)
diff --git a/vedirect.py b/vedirect.py
index 117fa5d..94509aa 100644
--- a/vedirect.py
+++ b/vedirect.py
@@ -1,5 +1,6 @@
 #!/usr/bin/python
 # -*- coding: utf-8 -*-
+# origin: https://github.com/karioja/vedirect
 
 import os, serial, argparse